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参数资料
| 型号： | ISL6124IR |
| 厂商： | INTERSIL CORP |
| 元件分类： | 电源管理 |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封装： | 4 X 4 MM, PLASTIC, QFN-24 |
| 文件页数： | 2/16页 |
| 文件大小： | 566K |
| 代理商： | ISL6124IR |
2
FN9005.4
June 10, 2005
Pinout
ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128 (QFN)
TOP VIEW
FIGURE 1. TYPICAL ISL6123 APPLICATION USAGE
AOUT
AIN
BIN
CIN
DIN
BOUT
COUT
DOUT
UVLO_B
UVLO_C
UVLO_A
UVLO_D
A
I
D
D
D
D
D
D
D
D
ENABLE
SYSRST#
GROUND
B
C
D
RESET#
V
DD
G
G
G
G
4mm X 4mm
1
2
3
4
5
6
18
17
16
15
14
13
24
23
22
21
20
19
7
8
9
10
11
12
Pin Descriptions
PIN #
PIN NAME
FUNCTION
DESCRIPTION
23
VDD
Chip Bias
Bias IC from nominal 1.5V to 5V
10
GND
Bias Return
IC ground
1
ENABLE_1/
ENABLE#_1
Input to start on/off
sequencing.
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
disabled for 10ms after UVLO is satisfied. ISL6123 has ENABLE. ISL6124, ISL6125, ISL6126 and
ISL6127 have ENABLE#.
Only ISL6128 has 2 ENABLE# inputs, 1 for each 2 channel grouping.
EN_1# for (A, B), and EN_2# for (C, D).
11
ENABLE#_2
24
RESET#
RESET# Output
RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for stabilization of
output voltages. RESET# will assert low upon UVLO not being satisfied or ENABLE/ENABLE# being
deasserted. The RESET outputs are open drain N channel FET and is guaranteed to be in the correct state
for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
RESET#_2 only exists on ISL6128 for (C, D) group I/O.
9
RESET#_2
20
UVLO_A
Under Voltage Lock
Out/Monitoring
Input
These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference and
are filtered to ignore short (<30μs) transients below programmed UVLO level.
12
UVLO_B
17
UVLO_C
14
UVLO_D
21
DLY_ON_A
Gate On Delay
Timer Output
Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each
cap is charged with 1μA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current
source providing delay to the associated FETs GATE turn-on.
These pins are NC on ISL6126 and ISL6127
8
DLY_ON_B
16
DLY_ON_C
15
DLY_ON_D
18
DLY_OFF_A
Gate Off Delay
Timer Output
Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a
capacitor to ground. Each cap is charged with a 1μA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down turning-off the FET.
These pins are NC on ISL6127
13
DLY_OFF_B
3
DLY_OFF_C
4
DLY_OFF_D
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6126IRZA | CAP 2.2UF 6.3V CERAMIC X5R 0805 |
| ISL6127IR | Power Sequencing Controllers |
| ISL6128IR | Power Sequencing Controllers |
| ISL6121LIBZA | Single Supply Integrated Current Limiting Controller |
| ISL6121LIBZA-T | Single Supply Integrated Current Limiting Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6124IR-T | 功能描述:IC CTRLR PWR SEQUENCE 4CH 24-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6124IRZA | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6124IRZA-T | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6125 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Power Sequencing Controllers |
| ISL6125 WAF | 制造商:Intersil Corporation 功能描述: |
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