参数资料
型号: ISL6146BFUZ-TK
厂商: Intersil
文件页数: 7/28页
文件大小: 0K
描述: IC OR CTRLR N-CH 1CH 8MSOP
标准包装: 1,000
应用: 电信/数据通信系统
FET 型: N 沟道
输出数: 1
内部开关:
延迟时间 - 关闭: 65ns
电源电压: 1 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
ISL6146
Electrical Specifications V CC = BIAS = 12V, unless otherwise stated. T A = +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
MIN
MAX
SYMBOL
t toffs
I ON
PARAMETERS
Slow Turn-off Time
Turn-On Current
TEST CONDITIONS
V IN = V BIAS = 12V, V GATE = 18V to 10V,
C GATE = 57nF
BIAS = 12V, VG = 0V
(Note 8)
TYP
58
1
(Note 8)
80
UNITS
μs
mA
BIAS = 12V, VG = 20V
0.15
mA
V VG_FLTr
V VG_FLTf
GATE to V IN Rising Fault Voltage
GATE to V IN Falling Fault Voltage
GATE > V IN , enabled, FLT output is high.
(Does not apply to ISL6146D and ISL6146E)
GATE > V IN , enabled, FLT output is low.
(Does not apply to ISL6146D and ISL6146E)
320
140
440
220
560
300
mV
mV
CONTROL AND REGULATION I/O
V Rr
V Rf
Reverse Voltage Detection
Rising V OUT Threshold
Reverse Voltage Detection
Falling V OUT Threshold
V OUT rising
V OUT falling
35
10
57
30
79
51
mV
mV
t Rs
Reverse Voltage Detection Response
Time
10
μs
V FWD_VR
V OS_HS
V TH(HS5k)
Amplifier Forward Voltage Regulation
HS Comparator Input Offset Voltage
ADJ Adjust Threshold with 5k to GND
ISL6146 controls voltage across FET V DS to
V FWD_VR during static forward operation at loads
resulting in Id*r DS(ON) < V FWD_VR
R ADJ = 5k ? to GND
11
-14
0.57
19
0.7
0.8
28
14
1.1
mV
mV
V
V TH(HS100k)
t HSpd
ADJ Adjust Threshold with 100k to GND R ADJ = 100k ? to GND
HS Comparator Response Time
V OUT > V IN , 1ns transition, 5V differential
10
40
170
95
mV
ns
V FWD_FLT
V FWD_FLT_HYS
V IN to V OUT Forward Fault Voltage
V IN to V OUT Forward Fault Voltage
Hysteresis
V IN > V OUT , GATE is fully on, FLT output is low
V IN > V OUT , GATE is fully on, FLT output is high
330
450
44
570
mV
mV
FAULT OUTPUT
I FLT_SINK
FAULT Sink Current
BIAS = 18V FAULT = 0.5V, V IN < V OUT , V GATE = V GL
5
9
mA
I FLT_LEAK
t FLT_L2H
t FLT_H2L
FAULT Leakage Current
FAULT Low to High Delay
FAULT High to Low Delay
FAULT = “V FLT_H ”, V IN > V OUT , V GATE = V IN + V GQP
GATE = V GQP to FAULT output is high
GATE = V IN to FAULT output is low
0.04
10
1.7
10
23
3
μA
μs
μs
ENABLE UVLO/OVP/ADJ INPUTS
VthRa
VthR_hysa
VthFb
VthF_hysb
VthFc
VthF_hysc
VthRc
VthR_hysc
t EN2GTER
ISL6146A/D EN Rising Vth
ISL6146A/D EN Vth Hysteresis
ISL6146B/E EN Falling Vth
ISL6146B/E EN Vth Hysteresis
ISL6146C OVP Falling Vth
ISL6146C OVP Vth Hysteresis
ISL6146C UVLO Rising Vth
ISL6146C UVLO Vth Hysteresis
EN/UVLO Rising to GATE Rising Delay
EN/OVP Falling to GATE Rising Delay
580
580
580
580
606
-90
606
+90
606
+90
606
-90
10
9
631
631
631
631
12
12
mV
mV
mV
mV
mV
mV
mV
mV
μs
μs
7
FN7667.4
April 26, 2013
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