参数资料
型号: ISL6160EVAL2
厂商: Intersil
文件页数: 1/7页
文件大小: 0K
描述: EVAL BOARD FOR ISL6160/HIP6006
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 5V
电流 - 输出: 3.5A
输入电压: 5V,12V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品: 2 个板
已用 IC / 零件: HIP6006,ISL6160
InfiniBand Class I Power Supply Using the
TM
ISL6160 and HIP6006 ICs
Application Note
September 2001
AN9959
Introduction
The InfiniBand architecture represents a significant evolution
of high-performance, switched-fabric interconnect systems.
The goal is to provide a high-performance, reliable, and
scalable way to connect high-end servers to each other and
to I/O subsystems, routers and switches that connect to the
world outside the data center.
Available from Intersil is the ISL6160, an evolution of IC power
sequencing, control and protection for InfiniBand I/O modules
(IM). The ISL6160 is designed to address the unique power
requirements of the InfiniBand (IB) industry initiative
providing independent power control of both the VB (bulk)
(+12V) and the VA (auxiliary) (+5V) power rails for a single
port. This device can be implemented in both IB Class I (non
isolated) and Class II (isolated) Power Topology
applications.
Intersil also provides the ISL6160EVAL2 concept evaluation
platform. The ISL6160EVAL2 is a complete InfiniBand Class I
(non isolated) power topology evaluation platform which
highlights the operation of the ISL6160 and the HIP6006 single
output PWM controller. See Figure 1 for a simplified block
diagram of the ISL6160EVAL2 platform. This evaluation
platform allows the InfiniBand Module (IM) power supply
designer to evaluate the concept of this design and apply this
concept to a specific IM power requirement. The evaluation
platform is configured for 5V Vout and 3.5A max Iout capability
supply rail from sudden in-rush current. During turn-on, the
external gate capacitor of the N-Channel MOSFET, Q3 (VB
switch) is charged with a 20 μ A current source resulting in a
programmable ramp (soft start turn-on). An internal charge
pump supplies the gate drive for the 12V VB supply switch
driving the MOSFET gate to VB +5V. Once the VB Secondary
Rail ramps to 10V the DC-DC_En pin is pulled high thus
enabling the accompanying voltage converter. The DC-DC
converter then provides a well regulated output voltage to the
load. For lab evaluation either an electronic or a passive load is
suitable for suppling a load current.
The ISL6160 VA undervoltage lockout feature prevents turn-on
of VA until VA_In > 2.5V. It then enables the VA soft start and
power up. The VA rising voltage output is a current limited ramp
so that both the inrush current and voltage slew rate are limited,
independent of load. This reduces supply droop due to surge
and eliminates the need for additional external EMI filters.
During operation, once a VA OC condition is detected the
output current is limited to 1A for 12ms to allow transient
conditions to pass. If VA is still in current limit after the current
limit period has elapsed, the output is then latched off. The VA
to the IM circuitry is latched off until reset by the disconnection
and reconnection of the IM from the chassis backplane.
VB_IN
where it exhibits an efficiency of 85%, all in a small 1.6 sq” area.
See Figure 11 for a complete ISL6160EVAL2 schematic.
Using the ISL6160EVAL2 Concept Board
VB_ON
VA_IN
DC-DC_ON
ISL6160
EN
UGATE
HIP6006
LGATE
Vout
R L
The ISL6160EVAL2 consists of a bus and load boards,
representing the IB chassis and IM respectively. The bus board
has terminals for VA and VB supplies. The load board with its
staggered length connector fingers to emulate the IM connector
then hot plugs into the socket as shown in Figure 2.
When the load board is inserted into the bus board, the stagger
on the connector fingers, first provides VX_RET, then VX
connections, and finally the shortest finger emulates the
VBx_En_L line connection.
Once VB_In is connected the VB control portion of the circuit is
biased but the VB Secondary Rail (TP1) is held off until the
ISL6160 VB_ON pin is signaled high. Local power enable
signaling is provided through the LCL_PWR_EN jumper either
as a hard tie ‘high’ with the jumper installed or through an
external input signal, on TP6 with the jumper removed. A single
logic gate IC, provides for the XORing of the VBxEN _L and
local power enable signals into the ISL6160 VB_ON pin. At the
C L
VAout
R LOAD
FIGURE 1. ISL6160EVAL2 BLOCK DIAGRAM
The VB Secondary Rail is enabled once the VB_ON (TP7) is
signalled high (through the assertion of the local power enable),
then the DC-DC En pin (TP2) is pulled high to VB. The RC
network of R4, R15 and C14 allows for setting the DC-DC
converter enabling signal level and ramp, thus customizing the
time to DC-DC enabling. Once the DC-DC is enabled the
output (TP3) ramps to 5V. The output is supplied with a banana
jack for connecting to an external active or passive load.
Figure 3 illustrates typical operational waveforms of the
ISL6160EVAL2. These are accessible through the labeled test
points (TPX) on the eval board.
time VB_ON is asserted high the ISL6160 turns on the VB
Secondary Rail in a soft start mode protecting the primary
1
See Figures 4 and 5 for ISL6160EVAL2 turn-on and turn-off
output voltage waveforms.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright ? Intersil Americas Inc. 2001, All Rights Reserved
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