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参数资料
| 型号： | ISL6208ACBZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/10页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRVR SYNC BUCK 8-SOIC |
| 标准包装： | 2,500 |
| 配置： | 高端和低端，同步 |
| 输入类型： | PWM |
| 延迟时间： | 26ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 33V |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
ISL6208A
The equation can be rewritten to solve for R DELAY as
follows:
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
( T DELAY ( ns ) – 5ns )
R DELAY ( k ? ) = ------------------------------------------------------
0.045
P = f sw ( 1.5V U Q U + V L Q L ) + I VCC V
CC
(EQ. 2)
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage rating
where f sw is the switching frequency of the PWM signal. V U
and V L represent the upper and lower gate rail voltage. Q U
and Q L is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The lV CC V CC product is the quiescent power
of the driver and is typically negligible.
C BOOT ≥ ------------------------
? V BOOT
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from the following equation:
Q GATE
(EQ. 1)
where Q GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ? V BOOT term is
defined as the allowable droop in the rail of the upper drive.
1000
900
800
700
600
500
400
Q U =100nC
Q L =200nC
Q U =50nC
Q L =100nC
Q U =50nC
Q L =50nC
Q U =20nC
Q L =50nC
As an example, suppose an upper MOSFET has a gate
charge, Q GATE , of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125 μ F is required.
300
200
100
The next larger standard value capacitance is 0.15 μ F. A
good quality ceramic capacitor is recommended.
0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
20nC
Q GATE = 100nC
FIGURE 11. POWER DISSIPATION vs FREQUENCY
0.0
0.0
0.1
0.2
0.3
0.4 0.5 0.6
0.7
0.8
0.9
1.0
? V BOOT_CAP (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125°C. The maximum
allowable IC power dissipation for the SO-8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
be performed to ensure safe operation at the desired
8
FN9272.0
February 15, 2006
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