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参数资料
| 型号： | ISL6208CB-T |
| 厂商： | INTERSIL CORP |
| 元件分类： | MOSFETs |
| 英文描述： | High Voltage Synchronous Rectified Buck MOSFET Driver |
| 中文描述： | 4 A HALF BRDG BASED MOSFET DRIVER, PDSO8 |
| 封装： | PLASTIC, MS-012AA, SOIC-8 |
| 文件页数： | 11/11页 |
| 文件大小： | 1692K |
| 代理商： | ISL6208CB-T |
9
FN9115.3
August 7, 2008
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The lVCC VCC product is the quiescent power
of the driver and is typically negligible.
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D2PAK and DPAK
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
FIGURE 9. POWER DISSIPATION vs FREQUENCY
FREQUENCY (kHz)
0
100
200
300
400
500
600
700
800
900
1000
0
200
400
600
800 1000 1200 1400 1600 1800 2000
P
O
WER
(m
W)
QU = 50nC
QL = 50nC
QU = 50nC
QL = 100nC
QU =100nC
QL = 200nC
QU = 20nC
QL =50nC
ISL6208
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相关代理商/技术参数 |
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| ISL6208CBZ | 功能描述:功率驱动器IC VER OF ISL6208CB IBM FAB RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| ISL6208CBZ-T | 功能描述:功率驱动器IC VER OF ISL6208CB-T - IBM FAB RoHS:否 制造商:Micrel 产品:MOSFET Gate Drivers 类型:Low Cost High or Low Side MOSFET Driver 上升时间: 下降时间: 电源电压-最大:30 V 电源电压-最小:2.75 V 电源电流: 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Tube |
| ISL6208CHRZ-T | 制造商:Intersil Corporation 功能描述:LEAD-FREE VERSION OF ISL6208CR - COST IMPROVEMENT - JAZZ FAB - Tape and Reel 制造商:Intersil Corporation 功能描述:IC MOSFET DRVR SYNC BUCK 8DFN |
| ISL6208CIRZ-T | 制造商:Intersil Corporation 功能描述:LEAD-FREE VERSION OF ISL6208CR - COST IMPROVEMENT - JAZZ FAB - Tape and Reel 制造商:Intersil Corporation 功能描述:IC MOSFET DRVR SYNC BUCK 8DFN |
| ISL6208CR | 功能描述:IC MOSFET DRVR SYNC BUCK 8-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:低端 输入类型:非反相 延迟时间:40ns 电流 - 峰:9A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:4.5 V ~ 35 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263 包装:管件 |
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