参数资料
| 型号： | ISL6217CV-T |
| 厂商： | Intersil |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM INTEL PENT 38-TSSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium? IMVP-IV，IMVP+ |
| 输入电压： | 5.5 V ~ 25 V |
| 输出数： | 1 |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
ISL6217
VID[0..5]
V CC_CORE
Current VID Code
< 600ns
Current Voltage Level
New VID Code
New Voltage Level
PGOOD
FIGURE 5.
VID[0..5]
STP_CPU#
(DSEN#)
HIGH
PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID Code remains the same
V CC_CORE
VID Command Voltage
VDeep Sleep
<30us
FIGURE 6.
VID[0..5]
STP_CPU#
(DSEN#)
CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID Code remains the same
Deeper Sleep Mode
DPRSLPVR
(DRSEN)
Short DPRSLP causes
V CC_CORE
V Deep Sleep
V Deeper Sleep
VCC-CORE
to ramp up
FIGURE 7.
VCORE RESPONSE FOR DEEPER SLEEP COMMAND
A logic low signal present on STPCPU# (pin DSEN#), with
a logic low signal on DPRSLPVR (pin DRSEN), signals the
ISL6217 to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin.
A logic high on DPRSLPVR, (pin DRSEN) with a logic low
signal on STPCPU# (pin DSEN#), signals the ISL6217
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in the “STV, DSV and
DRSV” section of this document.
Deep Sleep Enable-DSEN# and Deeper Sleep
Enable - DRSEN
Table 2 shows logic states controlling modes of operation.
Figure 6 and Figure 7 shows the timing for transitions
11
entering and exiting Deep Sleep Mode and Deeper Sleep
Mode. This is controlled by the system signals STPCPU#
and DPRSLPVR. ISL6217 pins DSEN#, (Deep Sleep
Enable #) and DRSEN, (Deeper Sleep Enable), are
connected to these 2 signals, respectively.
When DSEN# is logic high, and DRSEN is logic low, the
controller will operate in Active Mode and regulate the
output voltage to the VID commanded DAC voltage, minus
the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
When a logic low is detected at the DSEN# and DRSEN
pins, the controller will regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”. If the PWRCH
pin is connected to the DSEN# pin then the controller will
also switch to single channel operation.
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6218CVZA-T | IC CTRLR INTEL PENT M 38-TSSOP |
| ISL6219ACAZ-T | IC REG CTRLR BUCK PWM VM 28-QSOP |
| ISL6223CAZA | IC REG CTRLR BUCK PWM 20-SSOP |
| ISL6224CA-T | IC REG CTRLR BUCK PWM CM 16-SSOP |
| ISL6225CA-T | IC CTRLR DDR DRAM, SDRAM 28QSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6217CVZ | 功能描述:IC CTRLR PWM INTEL PENT 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6217CVZA | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV? and IMVP-IV+ |
| ISL6217CVZA-T | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV? and IMVP-IV+ |
| ISL6217CVZ-T | 功能描述:IC CTRLR PWM INTEL PENT 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6217EVAL2 | 制造商:Intersil Corporation 功能描述:PURCHASE ISL6216EVAL1, ISL6217EVAL2 OR ISL6218EVAL2 WITH IS - Bulk |
发布紧急采购，3分钟左右您将得到回复。