参数资料
型号: ISL6223CAZA
厂商: Intersil
文件页数: 8/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20-SSOP
标准包装: 580
PWM 型: 控制器
输出数: 2
频率 - 最大: 305kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 管件
the 5V supply rises. The PGOOD output stage is made up of
NMOS and PMOS transistors. On the rising V CC , the PMOS
device becomes active slightly before the NMOS transistor
pulls “down”, generating the slight rise in the PGOOD
voltage.
.
12V
SUPPLY
Note that Figure 5 shows the 12V battery voltage available
before the 5V supply to the ISL6223 has reached its
threshold level. If conditions were reversed and the 5V
supply was to rise first, the start-up sequence would be
different. In this case, the ISL6223 will sense an overcurrent
condition due to charging the output capacitors. The supply
DELAY TIME
PGOOD
V CORE
5V
SUPPLY
will then restart and go through the normal Soft-Start cycle.
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
PWM 1
OUTPUT
Fault Protection
The ISL6223 protects the microprocessor and the entire
power system from damaging stress levels. Within the
DELAY TIME
PGOOD
V CORE
ISL6223 both Overvoltage and Overcurrent circuits are
incorporated to protect the load and regulator.
Overvoltage
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE overvoltage condition is detected when the
VSEN pin goes above 2.35V.
EN
SWITCH
V IN = 12V
FIGURE 3. START-UP OF A SYSTEM OPERATING AT 200kHz
V COMP
The overvoltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can
only be reset by lowering and returning V CC high to initiate a
POR and Soft-Start sequence.
During a latched overvoltage, the PWM outputs will be
driven either low or three state, depending upon the VSEN
input. PWM outputs are driven low when the VSEN pin
detects that the CORE voltage is above 2.35V. This
condition drives the PWM outputs low, resulting in the lower
or synchronous rectifier MOSFETs to conduct and shunt the
CORE voltage to ground to protect the load.
DELAY TIME
PGOOD
V CORE
If after this event, the CORE voltage falls below 1.7V, the
PWM outputs will be three state. The HIP6601 family of
drivers pass the three state information along, and shut off
both upper and lower MOSFETs. This prevents “dumping” of
the output capacitors back through the lower MOSFETs,
avoiding a possibly destructive ringing of the capacitors and
output inductors. If the conditions that caused the
overvoltage still persist, the PWM outputs will be cycled
EN
SWITCH
V IN = 12V
FIGURE 4. START-UP A SYSTEM OPERATING AT 200kHz
8
between three state and V CORE clamped to ground, as a
hysteretic shunt regulator.
Undervoltage
The VSEN pin also detects when the CORE voltage falls
below 0.9V level. This causes PGOOD to go low, but has no
other effect on operation and is not latched. There is also
hysteresis in this detection point.
FN9013.3
July 9, 2008
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