参数资料
型号: ISL62381HRTZ
厂商: Intersil
文件页数: 14/23页
文件大小: 0K
描述: IC PWR SUPPLY CONTROLLER 32TQFN
标准包装: 60
应用: 电源控制器
电源电压: 5.5 V ~ 25 V
电流 - 电源: 150µA
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN(5x5)
包装: 管件
ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Theory of Operation
Four Output Controller
The ISL62381, ISL62382, ISL62381C and ISL62382C
generate four regulated output voltages, including two PWM
controllers and two LDOs. The two PWM channels are
shows PWM pulses being generated as V R traverses the
V COMP and V COMP + V W thresholds. The PWM switching
frequency is proportional to the slew rates of the positive and
negative slopes of V R; it is inversely proportional to the
voltage between V W and V COMP. Equation 3 illustrates how
to calculate the window size based on output voltage and
identical and almost entirely independent, with the exception
of sharing the GND pin. Unless otherwise stated, only one
individual channel is discussed, and the conclusion applies
frequency set resistor R W .
V W = g m ? V OUT ? ( 1 – D ) ? R W
(EQ. 3)
(EQ. 4)
F SW = ---------------------------------
(EQ. 5)
R W = ------------------------------------
to both channels.
PWM Modulator
The ISL62381, ISL62382, ISL62383, ISL62381C,
ISL62382C and ISL62383C modulator features Intersil’s R 3
technology, a hybrid of fixed frequency PWM control and
variable frequency hysteretic control. Intersil’s R 3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R 3 modulator synthesizes an AC signal V R ,
which is an analog representation of the output inductor
ripple current. The duty-cycle of V R is the result of charge
and discharge current through a ripple capacitor C R . The
current through C R is provided by a transconductance
amplifier g m that measures the VIN and VO pin voltages.
The positive slope of V R can be written as Equation 1:
Programming the PWM Switching Frequency
These controllers do not use a clock signal to produce
PWMs. The PWM switching frequency F SW is programmed
by the resistor R W that is connected from the FSET pin to
the GND pin. The approximate PWM switching frequency
can be expressed as written in Equation 4:
1
10 ? C R ? R W
For a desired F SW , the R W can be selected by Equation 5.
1
10 ? C R ? F SW
where C R = 17pF with ±20% error range. To smooth the
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with R W.
V RPOS = g m ? ( V IN – V OUT ) ? C R
(EQ. 1)
It is recommended that whenever the control loop
V RNEG = g m ? V OUT ? C R
The negative slope of V R can be written as Equation 2:
(EQ. 2)
Where g m is the gain of the transconductance amplifier.
compensation network is modified, F SW should be checked
for the correct frequency and if necessary, adjust R W .
Power-On Reset
These controllers are disabled until the voltage at the VIN
pin has increased above the rising power-on reset (POR)
RIPPLE CAPACITOR VOLTAGE V R
WINDOW VOLTAGE V W
(WRT V COMP )
ERROR AMPLIFIER
VOLTAGE V COMP
PWM
threshold voltage. The controller will be disabled when the
voltage at the VIN pin decreases below the falling POR
threshold.
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
These controllers use a digital soft-start circuit to ramp the
output voltage of each SMPS to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V COMP + V W is the higher threshold voltage. Figure 23
14
desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
t SS , starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
FN6665.5
May 13, 2011
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