参数资料
型号: ISL6244HRZ
厂商: Intersil
文件页数: 13/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 32-QFN
标准包装: 60
PWM 型: 电流/电压模式
输出数: 4
频率 - 最大: 4MHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 管件
ISL6244
TABLE 1. VOLTAGE IDENTIFICATION CODES
FEED-FORWARD RAMP COMPENSATION
d MAX ? V BATTERY
R ADJ2
------------------------------------------------- ? V
R ADJ1 + R ADJ2
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DAC
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
The ISL6244 features a V FF pin for setting the pulse width
modulator gain. The V FF voltage is set by a resistor divider
network from the battery voltage, as illustrated in Figure 18.
The V FF voltage sets the peak-to-peak voltage of the ramp
oscillator relative to the battery voltage. By feeding the
battery voltage forward, the pulse width modulation gain,
G mod , is independent of battery voltage, see Equation 5.
G mod = ----------------------------------------------------------------------------------------- = 0.75x10 = 7.5 (EQ. 5)
BATTERY
The ramp modulator gain is then set by the ratio of the
maximum duty cycle, d MAX , to the amount of attenuation
programmed by the resistor network on the V FF pin. For
typical applications, select R ADJ1 to be 9 times the value of
R ADJ2 for a 1/10 attenuation of the battery voltage, resulting
in a constant pulse width modulator gain of 7.5 over the
entire range of battery voltage (see note below).
NOTE: the V FF voltage must be bounded between 0.5V and 2.5V.
.
0
1
1
1
1
1.175
V COMP
PWM1
V BATTERY
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1.150
1.125
1.100
1.075
PWM
+
-
SAWTOOTH
SIGNAL
SAWTOOTH
GENERATOR
V FF
R ADJ1
R ADJ2
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
ISL6244 INTERNAL CIRCUITRY
FIGURE 18. BATTERY VOLTAGE FEED-FORWARD
COMPENSATION
LOAD-LINE REGULATION
Microprocessor load current demands change from near no-
load to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
The integrating compensation network shown in Figure 17
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6244 to include all variations in current
sources, amplifiers and the reference so that the output
voltage remains within the specified system tolerance of
shifted in a direction which works against the voltage spike.
The average current of all the active channels, I AVG , flows
out IOUT, see Figure 17. IOUT is connected to FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
± 1 %. The 1% does not include the VID offset tolerance or
any external component tolerances.
13
V DROOP = I AVG R FB
(EQ. 6)
FN9106.3
December 28, 2004
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