参数资料
| 型号： | ISL6262AIRZ |
| 厂商： | Intersil |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IC CORE CTRLR 2PHASE 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.3 V ~ 1.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6262A
The first current, labeled I SS , is given in the Table Electrical
Specifications on page 3 as 42μA. This current is used
during soft-start. The second current, I 2 sums with I SS to get
the larger of the two currents, labeled I GV in the
Table Electrical Specifications on page 3 . This total current
is typically 205μA with a minimum of 180μA.
The IMVP-6+ specification reveals the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP-6+ specification will
determine the choice of the SOFT capacitor, C SOFT , by
Equation 1.
noise immunity, the 3.3V supply should be decoupled to
digital ground rather than to analog ground.
CLK_EN# is logic level high at start-up until approximately
43μs after the V CC -core is in regulation at the Boot level.
Approximately 43μs after V CC -core are within regulation,
CLK_EN# goes low, triggering an internal timer for the
IMVP6_PWRGD signal. This timer allows IMVP-6_PWRGD
to go high approximately 6.8ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
C SOFT = ------------------------------------
I GV
SLEWRATE
(EQ. 1)
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
Using a SLEWRATE of 10mV/μs and the typical I GV value
given in the Electrical Specification table of 205μA, C SOFT is
as shown in Equation 2.
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6262A are connected to
C SOFT = 205 μ A ? ( 10mV ? 1 μ s )
(EQ. 2)
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are Vcc_sense and
A choice of 0.015μF would guarantee a SLEWRATE of
10mV/μs is met for the minimum I GV value given in the
Electrical Specification table. This choice of C SOFT will then
control the Start-Up slewrate as well. One should expect the
output voltage to slew to the Boot value of 1.2V at a rate
given by Equation 3.
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces. For
dV I SS 41 μ A
0.015 μ F
C SOFT
------- = ------------------- = ----------------------- = 2.8mV ? μ s
dt
(EQ. 3)
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
Selecting RBIAS
To properly bias the ISL6262A, a reference current is
established by placing a 147k Ω , 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate
10μA current source from which the OCSET reference
current can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262A provides a 3.3V logic output pin for
CLK_EN#. The 3V3 pin allows for a system 3.3V source to
be connected to separated circuitry inside the ISL6262A,
solely devoted to the CLK_EN# function. The output is a
3.3V CMOS signal with 4mA sourcing and sinking capability.
This implementation removes the need for an external
pull-up resistor on this pin, and due to the normal level of this
signal being a low, removes the leakage path from the 3.3V
supply to ground through the pull-up resistor. This reduces
the 3.3V supply current that would occur under normal
operation with a pull-up resistor and prolongs battery life. For
20
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode filters to analog ground on VSEN and RTN as shown in
Figure 37.
Intersil recommends the use of the R opn1 and R opn2
connected to V OUT and ground as shown in Figure 37.
These resistors provide voltage feedback in the event that
the system is powered up without a processor installed.
These resistors typically range from 20 to 100 Ω .
FN6343.1
December 23, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6262AIRZ-T | 功能描述:IC CORE CTRLR 2PHASE 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6262CRZ | 功能描述:直流/直流开关调节器 TWO-PHS DC/DC BUCK CNTRLR IMVP-6 4 8LD RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6262CRZR5242 | 制造商:Intersil Corporation 功能描述:53350B01 MASK ONLY AND DOT ON BRAND - Rail/Tube |
| ISL6262CRZ-T | 功能描述:直流/直流开关调节器 TWO-PHS DC/DC BUCK CNTRLR IMVP-6 4 8LD RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| ISL6262CRZ-TK | 功能描述:直流/直流开关调节器 TWO-PHS DC/DC BUCK CNTRLR IMVP-6 4 8LD RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
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