参数资料
| 型号： | ISL6263AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/19页 |
| 文件大小： | 0K |
| 描述： | IC PWN CTRLR SYNC BUCK 32QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，Intel IMVP-6 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.41 V ~ 1.29 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6263A
Functional Pin Descriptions
RBIAS (Pin 1) - Sets the internal 10μ A current reference.
Connect a 150k Ω ±1 % resistor from RBIAS to VSS.
SOFT (Pin 2) - Sets the output voltage slew-rate. Connect
an X5R or X7R ceramic capacitor from SOFT to VSS. The
SOFT pin is the non-inverting input of the error amplifier.
OCSET (Pin 3) - Sets the overcurrent threshold. Connect a
resistor from OCSET to VO.
VW (Pin 4) - Sets the static PWM switching frequency in
continuous conduction mode. Connect a resistor from VW to
COMP.
COMP (Pin 5) - Connects to the output of the control loop
error amplifier.
FB (Pin 6) - Connects to the inverting input of the control
loop error amplifier.
VDIFF (Pin 7) - Connects to the output of the VDIFF
differential-summing amplifier.
VSEN (Pin 8) - This is the V CC_SNS input of the processor
socket Kelvin connection. Connects internally to one of two
non-inverting inputs of the VDIFF differential-summing
amplifier.
RTN (Pin 9) - This is the V SS_SNS input of the processor
socket Kelvin connection. Connects internally to one of two
inverting inputs of the VDIFF differential-summing amplifier.
DROOP (Pin 10) - Connects to the output of the droop
differential amplifier and to one of two non-inverting inputs of
the VDIFF differential-summing amplifier.
DFB (Pin 11) - This is the feedback of the droop amplifier.
Connects internally to the inverting input of the droop
differential amplifier.
VO (Pin 12) - Connects to one of two inverting inputs of the
VDIFF differential-summing amplifier.
VSUM (Pin 13) - Connects to the non-inverting input of the
droop differential amplifier.
VIN (Pin 14) - Connects to the R 3 PWM modulator providing
input voltage feed-forward. For optimum input voltage
PHASE (Pin 19) - Current return path for the UGATE
high-side MOSFET gate driver. Detects the polarity of the
PHASE node voltage for diode emulation. Connect the
PHASE pin to the drains of the low-side MOSFETs.
PGND (Pin 20) - Current return path for the LGATE low-side
MOSFET gate driver. The PGND pin only conducts current
when LGATE pulls down. Connect the PGND pin to the
sources of the low-side MOSFETs.
LGATE (Pin 21) - Low-side MOSFET gate driver output.
Connect to the gate of the low-side MOSFET.
PVCC (Pin 22) - Input power supply for the low-side
MOSFET gate driver, and the high-side MOSFET gate
driver, via the internal bootstrap diode connected between
the PVCC and BOOT pins. Connect to +5VDC and decouple
with at least 1μF of an MLCC capacitor from the PVCC pin to
the PGND pin.
VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs.
VID0 input is the least significant bit (LSB) and VID4 input is
the most significant bit (MSB).
PMON (Pin 28) - A voltage signal proportional to the output
power of the converter.
VR_ON (Pin 29) - A high logic signal on this pin enables the
converter and a low logic signal disables the converter.
AF_EN (Pin 30) - Used in conjunction with VID0:VID4 and
FDE pins to program the diode-emulation and audio filter
behavior. Refer to Table 1.
PGOOD (Pin 31) - The PGOOD pin is an open-drain output
that indicates when the converter is able to supply regulated
voltage. Connect the PGOOD pin to a maximum of 5V
through a pull-up resistor.
FDE (Pin 32) - Used in conjunction with VID0:VID4 and
AF_EN pins to program the diode-emulation and audio filter
behavior. Refer to Table 1.
BOTTOM - Connects to substrate. Electrically isolated but
should be connected to VSS. Requires best practical
thermal coupling to PCB.
TABLE 1. DIODE-EMULATION MODE AND AUDIO-FILTER
transient response, connect near the drain of the high-side
MOSFETs.
RENDER
MODE
FDE AF_EN
DEM
STATUS
VOLTAGE
WINDOW
AUDIO
FILTER
VSS (Pin 15) - Analog ground.
VDD (Pin 16) - Input power supply for the IC. Connect to
+5VDC and decouple with at least a 1μF MLCC capacitor
from the VDD pin to the VSS pin.
BOOT (Pin 17) - Input power supply for the high-side
PERFORMANCE
SUSPEND
0
1
x
1
0
x
x
0
1
1
DISABLED
ENABLED
ENABLED
ENABLED
ENABLED
NOM
130% NOM
150% NOM
130% NOM
130% NOM
x
x
x
x
ENABLED
MOSFET gate driver. Connect an MLCC bootstrap capacitor
from the BOOT pin to the PHASE pin.
UGATE (Pin 18) - High-side MOSFET gate driver output.
Connect to the gate of the high-side MOSFET.
9
FN9284.3
July 8, 2010
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| ISL6263B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:5-Bit VID Single-Phase Voltage Regulator with Current Monitor for IMVP-6 Santa Rosa GPU Core |
| ISL6263BEVAL1Z | 功能描述:EVAL BAORD 1 FOR ISL6263B RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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