参数资料
| 型号： | ISL6267HRZ-T |
| 厂商： | Intersil |
| 文件页数： | 30/33页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 48TQFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（6x6） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页
ISL6267
TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER (Continued)
ISL6267
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
SYMBOL
ISUMN
ISUMP
VDD
VIN
PROG1
BOOT1
UGATE1
PHASE1
LGATE1
PWM3
VCCP
LGATE2
PHASE2
UGATE2
BOOT2
PWM2_NB
LGATE1_NB
PHASE1_NB
UGATE1_NB
BOOT1_NB
PROG2
NTC_NB
ISUMN_NB
ISUMP_NB
30
LAYOUT GUIDELINES
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two
signals traces in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71
to Core VR phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and
R72 to Core VR phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible,
route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center
of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the
inductor. The following drawings show the two preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
A capacitor (C16) decouples it to GND. Place it in close proximity to the controller.
A capacitor (C17) decouples it to GND. Place it in close proximity to the controller.
No special consideration.
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and
Q8) source pins instead of general copper.
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
No special consideration.
A capacitor (C22) decouples it to GND. Place it in close proximity to the controller.
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and
Q10) source pins instead of general copper.
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
No special consideration.
Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source
pins instead of general copper.
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
No special consideration.
Place the NTC thermistor close to the thermal source that is monitored to determine GT V CORE thermal
throttling. Usually it is placed close to Northbridge VR phase-1 high-side MOSFET.
Place the current sensing circuit in general proximity to the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to Northbridge VR phase-1 inductor (L1) so it senses the inductor temperature
correctly.
See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.
January 8, 2013
FN7801.1
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