参数资料
| 型号： | ISL62771HRTZ |
| 厂商： | Intersil |
| 文件页数： | 20/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR MULTIPHASE 40TQFN |
| 标准包装： | 60 |
| 系列： | Robust Ripple Regulator™ (R³) |
| 应用： | 控制器，AMD Fusion? SVI 2.0 CPU GPU |
| 输入电压： | 4.5 V ~ 25 V |
| 输出数： | 2 |
| 输出电压： | 0.006 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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ISL62771
TABLE 3. COMP and COMP_NB OUTPUT VOLTAGE OFFSET
value. See Figure 11 for a simple SVI interface timing diagram.
SELECTION (Continued)
RESISTOR VALUE [ k Ω ]
MIN 1% TOLERANCE MAX
TOLERANCE VALUE TOLERANCE
COMP
V CORE OFFSET
[mV]
COMP_NB
OFFSET
[mV]
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 5). Once the ENABLE input exceeds the rising
19.3
24.53
33.49
19.6
24.9
34.0
19.89
25.27
34.51
-18.75
-12.5
-6.25
37.5
25
12.5
threshold, the ISL62771 decodes and locks the decoded value
into an on-board hold register.
TABLE 5. PRE-PWROK METAL VID CODES
40.58
51.52
72.10
93.87
119.19
41.2
52.3
73.2
95.3
121
41.81
53.08
74.29
96.72
112.81
6.25
18.75
31.25
43.76
50
0
18.75
31.25
43.76
50
SVC
0
0
1
1
SVD
0
1
0
1
OUTPUT VOLTAGE
(V)
1.1
1.0
0.9
0.8
151.69
154
156.31
37.5
37.5
179.27
206.85
182
210
OPEN
184.73
213.15
25
12.5
0
25
12.5
0
The internal DAC circuitry begins to ramp Core and Northbridge
VRs to the decoded pre-PWROK Metal VID output level. The
digital soft-start circuitry ramps the internal reference to the
target gradually at a fixed rate of 10mV/μs. The controlled ramp
of all output voltage planes reduces in-rush current during the
CCM Switching Frequency
The Core and Northbridge VR switching frequency is set by the
programming resistor on COMP_NB. When the ISL62771 is in
continuous conduction mode (CCM), the switching frequency is
not absolutely constant due to the nature of the R 3 ? modulator.
As explained in the “Multiphase R3? Modulator” on page 14, the
effective switching frequency increases during load insertion and
decreases during load release to achieve fast response. Thus, the
switching frequency is relatively constant at steady state.
Variation is expected when the power stage condition, such as
input voltage, output voltage, load, etc. changes. The variation is
usually less than 10% and does not have any significant effect on
output voltage ripple magnitude. Table 4 defines the switching
frequency based on the resistor value used to program the
COMP_NB pin. Use the previous table related to COMP_NB to
determine the correct resistor value in these ranges to program
the desired output offset and switching frequency configuration.
TABLE 4. SWITCHING FREQUENCY SELECTION
soft-start interval. At the end of the soft-start interval, the PGOOD
and PGOOD_NB outputs transition high, indicating both output
planes are within regulation limits.
If the ENABLE input falls below the enable falling threshold, the
ISL62771 tri-states both outputs. PGOOD and PGOOD_NB are
pulled low with the loss of ENABLE. The Core and Northbridge VR
output voltages decay, based on output capacitance and load
leakage resistance. If bias to VDD falls below the POR level, the
ISL62771 responds in the manner previously described. Once
VDD and ENABLE rise above their respective rising thresholds,
the internal DAC circuitry re-acquires a pre-PWROK metal VID
code, and the controller soft-starts.
SVI Interface Active
Once the Core and Northbridge VRs have successfully
soft-started and PGOOD and PGOOD_NB signals transition high,
PWROK can be asserted externally to the ISL62771. Once
PWROK is asserted to the IC, SVI instructions can begin as the
controller actively monitors the SVI interface. Details of the SVI
FREQUENCY
[kHz]
300
400
COMP_NB RANGE
[k Ω ]
57.6 to OPEN
5.62 to 41.2
Bus protocol are provided in the “AMD Serial VID Interface 2.0
(SVI2) Specification”. See AMD publication #48022.
Once a VID change command is received, the ISL62771 decodes
the information to determine which VR is affected and the VID
target is determined by the byte combinations in Table 6. The
The controller monitors SVI commands to determine when to
enter power-saving mode, implement dynamic VID changes, and
shut down individual outputs.
AMD Serial VID Interface 2.0
The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the
AMD processor to directly control the Core and Northbridge
voltage reference levels within the ISL62771. Once the PWROK
signal goes high, the IC begins monitoring the SVC and SVD pins
for instructions. The ISL62771 uses a digital-to-analog converter
(DAC) to generate a reference voltage based on the decoded SVI
20
internal DAC circuitry steps the output voltage of the VR
commanded to the new VID level. During this time, one or more
of the VR outputs could be targeted. In the event either VR is
commanded to power-off by serial VID commands, the PGOOD
signal remains asserted.
If the PWROK input is de-asserted, then the controller steps both
the Core and the Northbridge VRs back to the stored pre-PWROK
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is re-asserted, then the ISL62771 SVI interface waits
for instructions.
FN8321.2
September 12, 2013
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| ISL62771HRTZ-T | 功能描述:IC PWM CTRLR MULTIPHASE 40TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:Robust Ripple Regulator™ (R³) 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL62771IRTZ | 功能描述:IC PWM CTRLR MULTIPHASE 40TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL62771IRTZ-T | 功能描述:IC PWM CTRLR MULTIPHASE 40TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:Robust Ripple Regulator™ (R³) 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL62773 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multiphase PWM Regulator for AMD Fusiona?￠ Desktop CPUs Using SVI 2.0 |
| ISL62773HRZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLR FOR AMD FUSION UP RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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