参数资料
型号: ISL62881CHRTZ-T
厂商: Intersil
文件页数: 22/37页
文件大小: 0K
描述: IC REG PWM SGL PHASE 28TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 4.5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 带卷 (TR)
配用: ISL62881CCPUEVAL2Z-ND - EVAL BOARD ISL62881CCPU 28QFN
ISL62881C, ISL62881D
Substitution of Equation 28 into Equation 27 gives
Equation 29:
T1(s) is the total loop gain of the voltage loop and the
droop loop. It always has a higher crossover frequency
V Rimon = ---------------------- × R imon
3I o × LL
V O
3I o × LL
R droop
Rewriting Equation 29 and application of full load
condition gives Equation 30:
V Rimon × R droop
R imon = ----------------------------------------------
(EQ. 29)
(EQ. 30)
than T2(s) and has more meaning of system stability.
T2(s) is the voltage loop gain with closed droop loop. It
has more meaning of output voltage response.
Design the compensator to get stable T1(s) and T2(s)
with sufficient phase margin, and output impedance
equal or smaller than the load line slope.
L
For example, given LL = 7m Ω , R droop = 3.08k Ω ,
V Rimon = 999mV at I omax = 22A, Equation 30 gives
R imon = 6.66k Ω .
V IN
Q1
GATE
DRIVER
Q2
C OUT
I O
A capacitor C imon can be paralleled with R imon to filter
the IMON pin voltage. The R imon C imon time constant is
the user’s choice. It is recommended to have a time
constant long enough such that switching frequency
ripples are removed.
Compensator
Figure 14 shows the desired load transient response
waveforms. Figure 20 shows the equivalent circuit of a
voltage regulator (VR) with the droop function. A VR is
LOAD LINE SLOPE
20 Ω
-
MOD EA
COMP +
VID
CHANNEL B
LOOP GAIN =
CHANNEL A
CHANNEL A
+
+
ISOLATION
TRANSFORMER
CHANNEL B
EXCITATION OUTPUT
equivalent to a voltage source (= VID) and output
impedance Z out (s). If Z out (s) is equal to the load line
slope LL, i.e. constant output impedance, in the entire
frequency range, V o will have square response when I o
has a square change.
NETWORK
ANALYZER
FIGURE 21. LOOP GAIN T1(s) MEASUREMENT SET-UP
Z out(s) = LL
i O
L
V O
VID
VR
LOAD
+
V O
-
V IN
Q1
GATE Q2
DRIVER
C OUT
I O
FIGURE 20. VOLTAGE REGULATOR EQUIVALENT
LOAD LINE SLOPE
20 Ω
Intersil provides a Microsoft Excel-based spreadsheet to
help design the compensator and the current sensing
network, so the VR achieves constant output impedance
as a stable system. Figure 23 shows a screenshot of the
spreadsheet.
A VR with active droop function is a dual-loop system
consisting of a voltage loop and a droop loop which is a
current loop. However, neither loop alone is sufficient to
-
MOD EA
COMP +
VID
CHANNEL B
LOOP GAIN =
CHANNEL A
CHANNEL A
NETWORK
ANALYZER
+
+
ISOLATION
TRANSFORMER
CHANNEL B
EXCITATION OUTPUT
describe the entire system. The spreadsheet shows two
loop gain transfer functions, T1(s) and T2(s), that
describe the entire system. Figure 21 conceptually shows
T1(s) measurement set-up and Figure 22 conceptually
shows T2(s) measurement set-up. The VR senses the
inductor current, multiplies it by a gain of the load line
slope, then adds it on top of the sensed output voltage
and feeds it to the compensator. T(1) is measured after
the summing node, and T2(s) is measured in the voltage
loop before the summing node. The spreadsheet gives
both T1(s) and T2(s) plots. However, only T2(s) can be
actually measured on an ISL62881C regulator.
22
FIGURE 22. LOOP GAIN T2(s) MEASUREMENT SET-UP
FN7596.0
March 8, 2010
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