参数资料
型号: ISL62882EVAL2Z
厂商: Intersil
文件页数: 27/42页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL62882
标准包装: 1
系列: Robust Ripple Regulator™ (R³)
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 0.3 ~ 1.5V
电流 - 输出: 60A
输入电压: 4.5 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL62882
ISL62882, ISL62882B
Optional Slew Rate Compensation Circuit For
1-Tick VID Transition
where C out is the total output capacitance.
In the mean time, the R vid -C vid branch current I vid time domain
expression is:
? ?
– t
dV fb
× C
R
I vid ( t ) = C vid × ------------ × ? 1 – e vid
Rdroop
Rvid Cvid
Vcore
------------------------------
vid ?
dt ? ?
? ?
(EQ. 39)
dV fb C out × LL dV core
C vid × ------------ = ------------------------ × ------------------
FB
Ivid
Idroop_vid
OPTIONAL
It is desired to let I vid (t) cancel I droop_vid (t). So there are:
R droop
(EQ. 40)
COMP
E/A
INTERNAL
Σ VDAC DAC
X1
VIDs
RTN
VSS
VID<0:6>
VSSSENSE
and:
R vid × C vid = C out × LL
The result is expressed in Equation 42:
(EQ. 41)
dV core
C out × LL
dt
C vid = ------------------------ × ------------------
R droop dV fb
dt
TO IC
VID<0:6>
Vfb
R vid = R droop
and:
------------------
------------
(EQ. 42)
(EQ. 43)
Ivid
Vcore
Idroop_vid
FIGURE 28. OPTIONAL SLEW RATE COMPENSATION CIRCUIT
FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
(12.5mV) per 2.5μs per, controlling output voltage V core slew
rate at 5mV/μs.
For example: given LL = 1.9m Ω , R droop = 2.87k Ω , C out = 1710μF,
dV core /dt = 5mV/μs and dV fb /dt = 15mV/μs, Equation 42 gives
R vid = 2.87k Ω and Equation 43 gives C vid = 377pF.
It’s recommended to select the calculated R vid value and start
with the calculated C vid value and tweak it on the actual board to
get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
R vid - C vid network is between the virtual ground and the real
ground, and hence has no effect on transient response.
Voltage Regulator Thermal Throttling
Figure 28 shows the waveforms of 1-tick VID transition. During
1-tick VID transition, the DAC output changes at approximately
54μA
64μA
15mV/μs slew rate, but the DAC cannot step through multiple
VIDs to control the slew rate. Instead, the control loop response
NTC
SW1
VR_TT#
speed determines V core slew rate. Ideally, V core will follow the FB
pin voltage slew rate. However, the controller senses the inductor
current increase during the up transition, as the I droop_vid
waveform shows, and will droop the output voltage V core
accordingly, making V core slew rate slow. Similar behavior occurs
during the down transition.
+
V NTC
-
R NTC
R s
1.24V
SW2
-
+
1.20V
To control V core slew rate during 1-tick VID transition, one can
add the R vid -C vid branch, whose current I vid cancels I droop_vid .
INTERNAL TO
ISL62882
?
------------------------- ?
? 1 – e C out × LL ?
I droop ( t ) = ------------------------ × ------------------ ×
R droop
When V core increases, the time domain expression of the
induced I droop change is
– t
C out × LL dV core
dt ? ?
? ?
27
(EQ. 38)
FIGURE 29. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE OF THE ISL62882
FN6890.4
June 21, 2011
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