参数资料
型号: ISL62882HRTZ-T
厂商: Intersil
文件页数: 12/42页
文件大小: 0K
描述: IC REG PWM 2PHASE BUCK 40TQFN
标准包装: 6,000
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
ISL62882, ISL62882B
Theory of Operation
Multiphase R 3 ? Modulator
VW
VW
Master Clock Circuit
Master
Vcrm
COMP
Master
COMP
Clock
Phase
Clock1
gmVo
Clock
Vcrm
Crm
Sequencer
Clock2
Master
Clock
Clock1
VW
VW
Clock1
Slave Circuit 1
S PWM1 Phase1
Q
R
L1
Vo
PWM1
Clock2
I L1
Co
PWM2
Vcrs1
gm
VW
Crs1
Slave Circuit 2
VW
Clock2
S
R
Q
PWM2 Phase2
L2
Vcrs1
I L2
Vcrs2
Crs2
Vcrs2
gm
FIGURE 7. R 3 ? MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
FIGURE 5. R 3 ? MODULATOR CIRCUIT
The ISL62882 is a multiphase regulator implementing Intel ?
IMVP-6.5? protocol. It can be programmed for 1- or 2-phase
operation for microprocessor core applications. It uses Intersil
patented R 3 ? (Robust Ripple Regulator?) modulator. The R 3 ?
VW
Vcrm
COMP
Master
Clock
Clock1
PWM1
Clock2
PWM2
VW
Vcrs2
Vcrs1
Hysteretic
Window
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 5 conceptually shows the ISL62882 multiphase R 3 ?
modulator circuit, and Figure 6 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal
to g m V o , where g m is a gain factor. C rm voltage V crm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the ISL62882 is in
2-phase mode, the master clock signal will be distributed to
Phases 1 and 2, and the Clock1 and Clock2 signals will be 180°
out-of-phase. If the ISL62882 is in 1-phase mode, the master
clock signal will be distributed to Phases 1 only and be the
Clock1 signal.
FIGURE 6. R 3 ? MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
12
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
voltage V Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C rs .
FN6890.4
June 21, 2011
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