参数资料
型号: ISL62882IRTZ
厂商: Intersil
文件页数: 22/42页
文件大小: 0K
描述: IC REG PWM 2PHASE BUCK 40TQFN
标准包装: 60
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
ISL62882, ISL62882B
i o
Vo
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
i o
RING
BACK
i L
Vo
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
i o
ISUM+
Vo
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C n IS TOO SMALL
Rntcs
Rntc
Rp
Cn.1
Rn
Cn.2 Vcn
i o
OPTIONAL
Ri
Rip
Cip
ISUM-
OPTIONAL
Vo
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN C n IS TOO LARGE
For example, given N = 2, R sum = 3.65k Ω , R p = 11k Ω ,
R ntcs = 2.61k Ω , R ntc = 10k Ω , DCR = 0.88m Ω and L = 0.36μH,
Equation 19 gives C n = 0.294μF.
Assuming the compensator design is correct, Figure 18 shows the
expected load transient response waveforms if C n is correctly
selected. When the load current I core has a square change, the
output voltage V core also has a square response.
If C n value is too large or too small, V Cn (s) will not accurately
represent real-time I o (s) and will worsen the transient response.
Figure 19 shows the load transient response when C n is too
small. V core will sag excessively upon load insertion and may
create a system failure. Figure 20 shows the transient response
when C n is too large. V core is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
22
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 21 shows the output voltage ring back problem during load
transient response. The load current i o has a fast step change, but
the inductor current i L cannot accurately follow. Instead, i L
responds in first order system fashion due to the nature of current
loop. The ESR and ESL effect of the output capacitors makes the
output voltage V o dip quickly upon load current change. However,
the controller regulates V o according to the droop current i droop ,
which is a real-time representation of i L ; therefore it pulls V o back
to the level dictated by i L , causing the ring back problem. This
phenomenon is not observed when the output capacitor have very
low ESR and ESL, such as all ceramic capacitors.
Figure 22 shows two optional circuits for reduction of the ring back.
C n is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 22 shows that two capacitors C n.1 and C n.2
are in parallel. Resistor R n is an optional component to reduce
the V o ring back. At steady state, C n.1 + C n.2 provides the desired
C n capacitance. At the beginning of i o change, the effective
capacitance is less because R n increases the impedance of the
C n.1 branch. As Figure 19 explains, V o tends to dip when C n is too
small, and this effect will reduce the V o ring back. This effect is
more pronounced when C n.1 is much larger than C n.2 . It is also
more pronounced when R n is bigger. However, the presence of
R n increases the ripple of the V n signal if C n.2 is too small. It is
recommended to keep C n.2 greater than 2200pF. R n value
usually is a few ohms. C n.1 , C n.2 and R n values should be
determined through tuning the load transient response
waveforms on an actual board.
FN6890.4
June 21, 2011
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