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| 型号： | ISL6307BCRZ |
| 厂商： | Intersil |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 43 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL6307B
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
For Positive Offset (connect R OFS to VCC):
1.6 × R REF
V OFFSET
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
R OFS = ------------------------------
For Negative Offset (connect R OFS to GND):
(EQ. 11)
0.4 × R REF
R OFS = ------------------------------
As shown in Figure 8, a current proportional to the average
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
V OFFSET
FB
(EQ. 12)
defined as
V DROOP = I AVG R FB
(EQ. 8)
DYNAMIC
DAC
VID D/A
The regulated output voltage is reduced by the droop voltage
R REF
V OUT = V REF – V OFFSET – ? ------------- ------------------ R FB ?
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
? I OUT R X ?
(EQ. 9)
? 6 R ISEN ?
E/A
REF
VCC
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor in the ISEN line,
N is the number of active channels, and R FB is the feedback
resistor. R X has a value of DCR, resistor or R DS(ON) , or
R SENSE depending on the sensing method.
1.6V
-
+
0.4V
+
-
ISL6307BCR
OR
GND
R OFS
OFS
Therefore the equivalent loadline impedance, i.e. Droop
VCC
GND
impedance, is equal to:
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
R LL = ------------ ------------------
R ISEN
N
R FB R X
(EQ. 10)
WITH ISL6307B
Dynamic VID
Output-Voltage Offset Programming
The ISL6307B allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6307B. The current flow through R REF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
20
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6307B checks the VID inputs six times every
switching cycle. If the VID code is found to have been
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between DAC level and the new VID
code changes, no change is made. If the VID code is more
than 1-bit higher or lower than the DAC (not recommended),
FN9225.0
March 9, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6307BCRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR COM TAPE AND RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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