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参数资料
| 型号： | ISL6307IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 23/34页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6307
soft-start ramp times, TD2 and TD4 can be calculated based
1.1xR SS
on the following equations.
TD2 = ------------------------ ( μ s )
6.25x25
(EQ. 15)
VR_RDY
( V VID – 1.1 ) xR SS
TD4 = ------------------------------------------------ ( μ s )
6.25x25
(EQ. 16)
UV
OC
-
+
100μA
I 1
For example, when VID is set to 1.5V and the Rss is set at
50%
REPEAT FOR
EACH CHANNEL
100k ? , the first soft-start ramp time TD2 will be 704μs and
the second soft-start ramp time TD4 will be 256μs.
VOUT, 500mV/DIV
DAC
REFERENCE
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC1
+
I AVG
100μA
I AVG
IOUT
+
VR_RDY, 5V/DIV
VDIFF
+
-
OV
OC2
-
2V
R IOUT
OVP
TD1
TD2
TD3 TD4
TD5
VID + 0.175V
FIGURE 12. POWER GOOD AND PROTECTION CIRCUITRY
EN_VTT, 1V/DIV
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID voltage.
When the output voltage at VSEN is below the undervoltage
500μs/DIV
FIGURE 11. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6307 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
power good signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time,TD5. TD5 is fixed delay with typical value at
85μs. VR_RDY will be pulled low when an undervoltage or
overvoltage condition is detected, or the controller is
disabled by a reset from EN_PWR, EN_VTT, POR, or VID
OFF-code.
23
threshold, VR_RDY gets pulled low. When the output
voltage comes back to 60% of the VID voltage, VR_RDY will
return back to high.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6307B
over voltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the 2nd soft-start, the OVP threshold is 1.275V. Once the
controller detects a valid VID input, the OVP trip point will be
changed to the VID voltage plus 175mV.
Two actions are taken by the ISL6307 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns) until the
voltage at VDIFF falls below 0.4V. This causes the Intersil
drivers to turn on the lower MOSFETs and pull the output
voltage below a level that might cause damage to the load.
The PWM outputs remain low until VDIFF falls below 0.4V,
and then PWM signals enter a high-impedance state. The
Intersil drivers respond to the high-impedance input by
turning off both upper and lower MOSFETs. If the
overvoltage condition reoccurs, the ISL6307 will again
command the lower MOSFETs to turn on. The ISL6307 will
continue to protect the load in this fashion as long as the
overvoltage condition recurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6307 is reset. Cycling the
FN9224.0
March 9, 2006
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