参数资料
| 型号： | ISL6308IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 3PHASE BUCK 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6308
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Thermal Resistance (Typical Notes 1, 2)
θ JA (°C/W)
θ JC (°C/W)
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, V BOOT . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, V PHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20μJ) to 24V (<200ns, V BOOT-PHASE = 12V)
Upper Gate Voltage, V UGATE . . . . V PHASE - 0.3V to V BOOT + 0.3V
V PHASE - 3.5V (<100ns Pulse Width, 2μJ) to V BOOT + 0.3V
Lower Gate Voltage, V LGATE . . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2μJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
40 Ld QFN Package . . . . . . . . . . . . . . 32 3.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ± 5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ± 5%
Ambient Temperature (ISL6308CRZ) . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature (ISL6308IRZ) . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θ JC , the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current
Gate Drive Bias Current
VCC POR (Power-On Reset) Threshold
PVCC POR (Power-On Reset) Threshold
Oscillator Frequency
Oscillator Ramp Amplitude (Note 3)
Maximum Duty Cycle (Note 3)
I VCC ; ENLL = high
I PVCC ; ENLL = high; all gate outputs open, F sw = 250kHz
VCC Rising
VCC Falling
PVCC Rising
PVCC Falling
F SW
V P-P
12
0.4
4.25
3.75
4.25
3.75
225
-
-
15
0.8
4.38
3.88
4.38
3.88
250
1.50
66.6
18
1.2
4.47
4.00
4.47
4.00
275
-
-
mA
mA
V
V
V
V
kHz
V
%
CONTROL THRESHOLDS
ENLL Rising Threshold
ENLL Hysteresis
0.595
54
0.630
61
0.670
68
V
mV
ENLL Pull-up current
COMP Shutdown Threshold
ENLL = 1V
COMP Falling
-0.5
0.1
-1.4
0.25
-3.0
0.4
μA
V
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V)
System Accuracy (DAC = 1.2V, 1.50V)
DAC Input Low Voltage (REF0, REF1)
DAC Input High Voltage (REF0, REF1)
Minimum External Reference (Note 4)
Maximum External Reference (Note 4)
OFS Sink Current Accuracy (Negative Offset)
DROOP connected to IREF
DROOP connected to IREF
REF pin input
REF pin input
R OFS = 30k Ω from OFS to VCC
-0.8
-0.5
-
0.8
-
-
47.5
-
-
-
-
0.6
1.75
50.0
0.8
0.5
0.4
-
-
-
52.5
%
%
V
V
V
V
μA
OFS Source Current Accuracy (Positive Offset) R OFS = 10k Ω from OFS to GND
47.5
50.0
52.5
μA
5
FN9208.4
September 30, 2008
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