参数资料
| 型号： | ISL6312CRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 27/35页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6312
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 25, 26, 27 and 28. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
PVCC
BOOT
C GD
D
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
R HI1
R LO1
UGATE
G
R G1
R GI1
C DS
Package Power Dissipation
C GS
Q1
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
S
PHASE
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
C DS
Q2
When designing the ISL6312 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
average driver current can be estimated with Equations 29
and 30, respectively.
S
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 29)
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
the MOSFETs. Figures 16 and 17 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P DR , can be roughly
estimated as:
I DR = ? --- ? Q G1 ? N
3
? 2
Q1
(EQ. 30)
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
3
P Qg_Q1
P BOOT = ---------------------
(EQ. 31)
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
R HI1 + R EXT1 R LO1 + R EXT1 ?
?
P DR_LOW = ? ? ? ---------------------
? R HI2 R LO2 ? P Qg_Q2
? R HI2 + R EXT2
R LO2 + R EXT2 ?
2
In Equations 29 and 30, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs per
phase, respectively; N PHASE is the number of active
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
300kHz.
27
? R HI1 R LO1 ? P Qg_Q1
3
-------------------------------------- + ----------------------------------------
N N
R GI1 R GI2
R EXT1 = R G1 + ------------- R EXT2 = R G2 + -------------
Q1 Q2
FN9289.6
February 1, 2011
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