参数资料
| 型号： | ISL6312IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/35页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6312
V OUT = V REF – V OFS – V DROOP
(EQ. 8)
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
The ISL6312 incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference
point resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through
an external resistor.
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as:
V DROOP = I AVG ? R FB (EQ. 9)
EXTERNAL CIRCUIT
COMP
ISL6312 INTERNAL CIRCUIT
The regulated output voltage is reduced by the droop voltage
VID DAC
V DROOP . The output voltage as a function of load current is
derived by combining Equations 7, 8, and 9.
V OUT = V REF – V OFS – ? ------------- ? ------------------ ? R FB ?
C C
REF
1k
? I OUT DCR ?
? N R ISEN ?
(EQ. 10)
ERROR
-
R C
R FB
C REF
FB
IDROOP
+
(V DROOP + V OFS )
-
VDIFF
+
AMPLIFIER
I OFS
I AVG
V COMP
In Equation 10, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the internal sense resistor
connected to the ISEN+ pin, R FB is the feedback resistor, N
is the active channel number, and DCR is the Inductor DCR
value.
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to Equation 11:
R LL = ------------ ? ------------------
R ISEN
V OUT +
VSEN
+
R FB DCR
N
(EQ. 11)
V OUT -
RGND -
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a
precisely-controlled output resistance. This dependence of
output voltage on load current is often termed “droop” or
“load line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
Output-Voltage Offset Programming
The ISL6312 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the FB pin.
If R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (I OFS x R FB ). These functions are
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
R OFS = --------------------------
V OFFSET
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
19
For Negative Offset (connect R OFS to GND):
0.4 ? R FB
V OFFSET
For Positive Offset (connect R OFS to VCC):
1.6 ? R FB
R OFS = --------------------------
(EQ. 12)
(EQ. 13)
FN9289.6
February 1, 2011
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