参数资料
型号: ISL6315CRZ-T
厂商: Intersil
文件页数: 8/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 255kHz
占空比: 67%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6315
INTERLEAVING
The switching of each channel in a ISL6315-based converter
the designer to use fewer or less costly output capacitors
(should output ripple be an important design parameter).
L ? f S ? V
is timed to be symmetrically out of phase with the other
channel. As a result, the two-phase converter has a
combined ripple frequency twice the frequency of one of its
phases. In addition, the peak-to-peak amplitude of the
combined inductor currents is proportionately reduced.
Increased ripple frequency and lower ripple amplitude
generally translate to lower per-channel inductance and
lower total output capacitance for a given set of performance
specifications.
I L1 + I L2
I L2
( V IN – N ? V OUT ) ? V OUT
I P-P = --------------------------------------------------------------------
IN
C IN CURRENT
Q1 D-S CURRENT
Q3 D-S CURRENT
(EQ. 5)
PWM2
I L1
FIGURE 3. INPUT CAPACITOR CURRENT AND INDIVIDUAL
PWM1
FIGURE 2. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 2-PHASE CONVERTER
Figure 2 illustrates the additive effect on output ripple
frequency. The two channel currents (I L1 and I L2 ), combine
to form the AC ripple current and the DC load current. The
ripple component has two times the ripple frequency of each
individual channel current.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
CHANNEL CURRENTS IN A 2-PHASE
CONVERTER
Another benefit of interleaving is the reduction of input ripple
current. Input capacitance is determined in a large part by
the maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 3 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
Figure 12, part of the section entitled “Input Capacitor
Selection” on page 18, can be used to determine the input-
capacitor RMS current based on load current and duty cycle.
The figure is provided as an aid in determining the optimal
( V IN – V OUT ) ? V OUT
L ? f S ? V
I L , P-P = ----------------------------------------------------------
IN
(EQ. 4)
input capacitor solution.
PWM OPERATION
One switching cycle for the ISL6315 is defined as the time
V IN and V OUT are the input and output voltages,
respectively, L is the single-channel inductor value, and f S is
the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Peak-to-peak ripple current, I P-P ,
decreases by an amount proportional to the number of
channels. Output-voltage ripple is a function of capacitance,
capacitor equivalent series resistance (ESR), and inductor
ripple current. Reducing the inductor ripple current allows
8
between consecutive PWM pulse terminations (turn-off of
the upper MOSFET on a channel). Each cycle begins when
a switching clock signal commands the upper MOSFET to
go off. The other channel’s upper MOSFET conduction is
terminated 1/2 of a cycle later.
Once a channel’s upper MOSFET is turned off, the lower
MOSFET remains on for a minimum of 1/3 cycle. This forced
off time is required to assure an accurate current sample.
Following the 1/3-cycle forced off time, the controller enables
the upper MOSFET output. Once enabled, the upper
MOSFET output transitions high when the sawtooth signal
crosses the adjusted error-amplifier output signal, as
FN9222.1
July 18, 2007
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