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参数资料
| 型号： | ISL6315IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 255kHz |
| 占空比： | 67% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6315
is important to have a symmetrical layout, preferably with the
controller equidistantly located from the two power trains it
controls. Equally important are the gate drive lines (UGATE,
LGATE, PHASE): since they drive the power train MOSFETs
using short, high current pulses, it is important to size them
accordingly and reduce their overall impedance. Equidistant
placement of the controller to the two power trains also helps
keeping these traces equally long (equal impedances,
resulting in similar driving of both sets of MOSFETs).
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C IN ,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the high-frequency decoupling capacitors (ceramic)
as close as practicable to the decoupling target, making use
of the shortest connection paths to any internal planes, such
+12V IN
L IN
as vias to GND immediately next, or even onto the capacitor
solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC. Locate the bypass capacitors, C BP ,
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a high-
impedance circuit loop, sensitive to EMI pick-up. It is
important to place the R ISEN resistor close to the respective
terminal of the ISL6315.
A multi-layer printed circuit board is recommended. Figure 10
shows the connections of the critical components for one
output channel of the converter. Note that capacitors C xxIN
and C xxOUT could each represent numerous physical
capacitors. Dedicate one solid layer, usually the one
underneath the component side of the board, for a ground
+5V IN
(C F1 )
VCC
(C F2 )
PVCC
(C HFIN1 )
C BIN1
DACSEL/VID12
VID4
VID3
VID2
VID1
VID0
VRM10
BOOT1
UGATE1
PHASE1
C BOOT1
Q1
Q2
L OUT1
R ISEN
ISEN
LGATE1
BOOT2
V OUT
R’ OFS
SSEND
ENLL
ISL6315
C BOOT2
OFS
C BIN2
C BOUT
(C HFOUT )
R OFS
COMP
UGATE2
PHASE2
Q3
(C HFIN2 )
C 2
R 2
C 1
LGATE2
Q4
L OUT2
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION PATH)
PGND
FB
R 1
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
GND
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
17
FN9222.1
July 18, 2007
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