参数资料
型号: ISL6323AIRZ
厂商: Intersil
文件页数: 20/36页
文件大小: 0K
描述: IC PWM CTRLR SYNC BUCK DL 48QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6323A
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
VDIFF
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied ground, a
-
V OFS
+
R FB
VREF
E/A
current eight times the average current of all active
channels, 8*I AVG , flows from FB through a load-line
regulation resistor R FB . The resulting voltage drop across
R FB is proportional to the output current, effectively creating
an output voltage droop with a steady-state value defined as
in Equation 12:
I OFS
FB
V DROOP = I AVG ? R FB
(EQ. 12)
VCC
R OFS
-
1.6V
The regulated output voltage is reduced by the droop voltage
+
+
V DROOP . The output voltage as a function of load current is
shown in Equation 13.
OFS
ISL6323A
-
0.3V
V OUT = V REF – V OFS – ? ------------- ? DCR ? ? ---------- ? --------------- ? ? K ? R FB ?
R SET ?
? 3
? I OUT 400 1 ?
? N ?
(EQ. 13)
In Equation 13, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, K I is an internal gain determined by the
R SET resistor connected to the RSET pin (K I is defined in
GND
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
V OUT
VCC
Equation 10), K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
+
V OFS
-
R FB
VREF
active channels, and DCR is the Inductor DCR value.
Output-Voltage Offset Programming
The ISL6323A allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the FB pin
and out of the OFS pin. If R OFS is connected to ground, the
FB
I OFS
E/A
voltage across it is regulated to 0.3V, and I OFS flows into the
-
1.6V
OFS pin and out of the FB pin. The offset current flowing
+
+
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I OFS x R FB ). These functions are shown in Figures 9 and
R OFS
OFS
GND
ISL6323A
-
GND
0.3V
VCC
Once the desired output offset voltage has been determined,
use the formulas in Equations 14 and 15 to set R OFS :
For Positive Offset (connect R OFS to GND):
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
R OFS = --------------------------
R OFS = --------------------------
0.3 × R FB
V OFFSET
For Negative Offset (connect R OFS to VCC):
1.6 × R FB
V OFFSET
20
(EQ. 14)
(EQ. 15)
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323A through
either the PVI or SVI interface. The ISL6323A manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6323A begins slewing the
DAC at 3.25mV/μs until the DAC and target voltage are
FN6878.1
May 12, 2010
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