参数资料
| 型号： | ISL6324IRZ |
| 厂商： | Intersil |
| 文件页数： | 32/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6324
.
-------------------------------- > f 0
C 2 (OPTIONAL)
Case 1:
1
2 ? π ? L ? C
R C = R FB ? ----------------------------------------------------------
0.66 ? V
2 ? π ? V P-P ? R FB ? f 0
R C
C C
COMP
FB
2 ? π ? f 0 ? V P-P ? L ? C
IN
0.66 ? V IN
C C = ------------------------------------------------------
ISL6324
-------------------------------- ≤ f 0 < -------------------------------------
R FB
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
V P-P ? ( 2 ? π ) 2 ? f 02 ? L ? C
R C = R FB ? ------------------------------------------------------------------
( 2 ? π ) 2 ? f 02 ? V P-P ? R FB ? L ? C
VSEN
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6324 CIRCUIT
Since the system poles and zero are affected by the values
0.66 ? V IN
0.66 ? V IN
C C = ---------------------------------------------------------------------------------------
(EQ. 49)
f 0 > -------------------------------------
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Case 3:
1
2 ? π ? C ? ESR
R C = R FB ? ----------------------------------------------
2 ? π ? V P-P ? R FB ? f 0 ? L
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f 0 .
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
2 ? π ? f 0 ? V P-P ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
C C = ------------------------------------------------------------------
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 24, provides the
necessary compensation.
C 2
equations for the compensation components.
In Equation 49, L is the per-channel filter inductance divided
R C
C C
COMP
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
FB
the bulk output filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude as described in the
Once selected, the compensation values in Equation 49
C 1
R 1
R FB
VSEN
ISL6324
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 49 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 23). Keep
a position available for C 2 , and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
32
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f HF . This pole can be used for added
noise rejection or to assure adequate attenuation at the error
amplifier high-order pole and zero frequencies. A good general
rule is to choose f HF = 10f 0 , but it can be higher if desired.
Choosing f HF to be lower than 10f 0 can cause problems with
too much phase shift below the system bandwidth as shown in
Equation 50.
FN6518.2
September 25, 2008
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| ISL6324IRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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