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参数资料
| 型号： | ISL6329IRZ |
| 厂商： | Intersil |
| 文件页数： | 29/38页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 60QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6329
divided into separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-recovery
charge, Q rr , and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does not
conduct any portion of the inductor current until the voltage at
the phase node falls below ground. Once the lower MOSFET
begins conducting, the current in the upper MOSFET falls to zero
as the current in the lower MOSFET ramps up to assume the full
inductor current. In Equation 25, the required time for this
MOSFETs. The Δ V BOOT_CAP term is defined as the allowable
droop in the rail of the upper gate drive.
1.6
1.4
1.2
1.0
I PP
I M
P UP , 1 ≈ V IN ? ? ------ + --------- ? ? ? ---- 1 ? ? f S
? t ?
commutation is t 1 and the approximated associated power loss
is P UP,1 .
(EQ. 25)
? N 2 ? ? 2 ?
0.8
0.6
0.4
Q GATE = 100nC
P UP , 2 ≈ V IN ? ? ------ – --------- ? ? ? ---- 2 ? ? f S
20nC
P UP , 3 = V IN ? Q rr ? f S
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 26, the approximate
power loss is P UP,2 .
? I M I PP ? ? t ? (EQ. 26)
? N 2 ? ? 2 ?
A third component involves the lower MOSFET reverse-recovery
charge, Q rr . Since the inductor current has fully commutated to
the upper MOSFET before the lower-MOSFET body diode can
recover all of Q rr , it is conducted through the upper MOSFET
across VIN. The power dissipated as a result is P UP,3 .
(EQ. 27)
Finally, the resistive part of the upper MOSFET is given in
Equation 28 as P UP,4 .
50nC
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Δ V BOOT_CAP (V)
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Gate Drive Voltage Versatility
The ISL6329 provides the user flexibility in choosing the gate
drive voltage for efficiency optimization. The controller ties the
upper and lower drive rails together. Simply applying a voltage
from 5V up to 12V on PVCC sets both gate drive rail voltages
simultaneously.
Package Power Dissipation
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? ? ------ ? ? d + ----------
? N ? 12
2
(EQ. 28)
When choosing MOSFETs, it is important to consider the amount
of power being dissipated in the integrated drivers located in the
controller. Since there are a total of three drivers in the controller
C BOOT_CAP ≥ --------------------------------------
Δ V BOOT_CAP
Q G1 ? PVCC
Q GATE = ------------------------------------ ? N Q1
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
(EQ. 30)
I DR = ? --- ? Q G1 ? N + Q G2 T N Q2 ? ? N PHASE ? F SW + I Q (EQ. 31)
The total power dissipated by the upper MOSFET at full load can
now be approximated as the summation of the results from
Equations 25, 26, 27 and 28. Since the power equations depend
on MOSFET parameters, choosing the correct MOSFETs can be an
iterative process involving repetitive solutions to the loss
equations for different MOSFETs and different switching
frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the PHASE node.
This reduces voltage stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 4V and its capacitance value can be chosen from
Equation 29:
Q GATE
(EQ. 29)
V GS1
where Q G1 is the amount of gate charge per upper MOSFET at
V GS1 gate-source voltage and N Q1 is the number of control
29
package, the total power dissipated by all three drivers must be
less than the maximum allowable power dissipation for the QFN
package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 34 for
thermal transfer improvement suggestions.
When designing the ISL6329 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to the
gate charge of MOSFETs and the integrated driver’s internal
circuitry and their corresponding average driver current can be
estimated with Equations 30 and 31, respectively.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
3
? 2 Q1 ?
FN7800.0
April 19, 2011
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| ISL6329IRZ-T | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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| ISL6333AEVAL1Z | 制造商:Intersil Corporation 功能描述: |
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