参数资料
| 型号： | ISL6334DIRZ |
| 厂商： | Intersil |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE VR11.1 40QFN |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
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ISL6334D
FB
of R REF and C REF network and t VID is given by Equation 10.
C REF R REF = t VID
During dynamic VID transition and VID step-up, the
(EQ. 10)
DYNAMIC
DAC
overcurrent trip point increases by 140% to avoid falsely
E/A
VID D/A
R REF
REF
C REF
VCC
OR
GND
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50μs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
1.6V
-
+
+
R OFS
logic high.
Enable and Disable
VCC
0.4V
-
GND
ISL6334D
OFS
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334D
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Once the desired output offset voltage has been determined,
use Equations 8 and 9 to calculate R OFS :
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
R OFS = ------------------------------
R OFS = ------------------------------
For Positive Offset (connect R OFS to VCC):
1.6 × R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 × R REF
V OFFSET
(EQ. 8)
(EQ. 9)
threshold is reached, proper operation of all aspects of
the ISL6334D are guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
ISL6334D will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” table beginning on page 6).
2. The ISL6334D features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6334D in shutdown until the voltage at EN_PWR
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R REF and C REF , as shown in Figure 7, can be
used. The selection of R REF is based on the desired offset
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t VID , the relationship between the time constant
17
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver reaches its POR level before the ISL6334D
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6334D with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions previously mentioned are satisfied,
ISL6334D begins the soft-start and ramps the output voltage
to 1.1V first. After remaining at 1.1V for some time, ISL6334D
reads the VID code at VID input pins. If the VID code is valid,
ISL6334D will regulate the output to the final VID setting. If the
VID code is OFF code, ISL6334D will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
FN6802.3
November 22, 2013
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| ISL6334DIRZ-T | 功能描述:IC CTRLR PWM 4PHASE VR11.1 40QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334IRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334IRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336ACRZ | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6336ACRZ-T | 功能描述:IC CTRLR PWM 6PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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