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| 型号： | ISL6341AIRZ |
| 厂商： | Intersil |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-TDFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 660kHz |
| 占空比： | 75% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 管件 |
ISL6341, ISL6341A, ISL6341B, ISL6341C
G MOD ( f ) = ------------------------------ ? ----------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( E + D ) ? C + s ( f ) ? L ? C
1 + s ( f ) ? 2 ? 1
1 + s ( f ) ? ( 1 + 3 ) ? 3
R C ? R ? C 1 ? C 2 ? ?
R 2 = ---------------------------------------------
d MAX ? V IN ? F LC
1
F P1 = --------------------------------------------
F Z1 = ------------------------------ C C
2 π ? 2 ? --------------------
(EQ. 9)
1
F Z2 = ------------------------------------------------
R R C F P2 = ------------------------------
The compensation network consists of the error amplifier
(internal to the ISL6341x) and the external R 1 to R 3 , C 1 to C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of f SW ) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F 0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
C 3 ) in Figure 13. Use the following guidelines for locating the
poles and zeros of the compensation network:
4. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate the
value for R 2 for desired converter bandwidth (F 0 ). If
setting the output voltage via an offset resistor connected
to the FB pin (R o in Figure 13), the design procedure can
be followed as presented in Equation 4.
V OSC ? R 1 ? F 0
(EQ. 4)
5. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
d MAX ? V IN 1 + s ( f ) ? E ? C
2
R C
R C C
G FB ( f ) = --------------------------------------------------- ?
s ( f ) ? 1 ? ( 1 + 2 )
R R C
? ------------------------------------------------------------------------------------------------------------------------
( 1 + s ( f ) ? 3 ? 3 ) ? ? 1 + s ( f ) ? 2 ? ? -------------------- ? ?
? ? C 1 + C 2 ? ?
G CL ( f ) = G MOD ( f ) ? G FB ( f ) where , s ( f ) = 2 π ? f ? j
(EQ. 8)
COMPENSATION BREAK FREQUENCY EQUATIONS
1
2 π ? 2 ? 1 R 1 ? 2
C C
1 + 2
1
2 π ? ( 1 + 3 ) ? 3 2 π ? 3 ? 3
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
C 1 = -----------------------------------------------
1
2 π ? R 2 ? 0.5 ? F LC
(EQ. 5)
2 π ? R 2 ? C 1 ? F CE – 1
? R ?
20 log ? -------- ?
? R ?
6. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 6)
0
2
? 1 ?
d MAX ? V IN
20 log ---------------------------------
V OSC
7. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below f SW (typically, 0.5 to 1.0
times f SW ). f SW represents the switching frequency.
Change the numerical factor to reflect desired placement
G CL
G MOD
G FB
of this pole. Placement of F P2 lower in frequency helps
LOG
F LC
F CE
F 0
FREQUENCY
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
FIGURE 14. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 14 shows an asymptotic plot of the DC/DC converter’s
R 3 = --------------------
f SW
C 3 = -----------------------------------------------
R 1
----------- – 1
F LC
1
2 π ? R 3 ? 0.7 ? f SW
(EQ. 7)
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previous guidelines should yield
a compensation gain similar to the curve plotted. The open loop
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier ’s open-loop gain. Verify phase margin results and
adjust as necessary. Equations 8 and 9 describe the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
14
error amplifier gain bounds the compensation gain. Check the
compensation gain at F P2 against the capabilities of the error
amplifier. The closed loop gain, G CL , is constructed on the log-
log graph of Figure 14 by adding the modulator gain, G MOD (in
dB), to the feedback compensation gain, G FB (in dB). This is
equivalent to multiplying the modulator transfer function and the
compensation transfer function and then plotting the resulting
gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
FN6538.2
December 2, 2008
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| ISL6341AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6341BCRZ | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6341BCRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6341BIRZ | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6341BIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 10-TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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