参数资料
| 型号： | ISL6363IRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER VR12 48TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR12 |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.25 V ~ 1.52 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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ISL6363
Gate Driver Timing Diagram
PWM
t LGFUGR
t RU
t FU
UGATE
LGATE
1V
1V
t FL
t UGFLGR
t RL
Theory of Operation
VW
MASTER CLOCK CIRCUIT
MASTER
Multiphase R3 Modulator
The ISL6363 is a multiphase regulator implementing Intel’s?
VR12? protocol. It has two voltage regulators, VR1 and VR2, on
MASTER
CLOCK
gmVo
COMP
Vcrm
Crm
CLOCK
Phase
Sequencer
Clock1
Clock2
Clock3
one chip. VR1 can be programmed for 1, 2, 3, or 4-phase
SLAVE CIRCUIT 1
operation, and VR2 is dedicated for 1-phase operation. The
following description is based on VR1, but also applies to VR2
VW
Clock1
S
R
Q
PWM1 Phase1
L1
Vo
because the same architecture is implemented.
I L1
Co
The ISL6363 uses Intersil’s patented R3 (Robust Ripple Regulator)
modulator. The R3 modulator combines the best features of fixed
Crs1
Vcrs1
gm
frequency PWM and hysteretic PWM while eliminating many of
their shortcomings. Figure 3 conceptually shows the multiphase
R3 modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
VW
SLAVE CIRCUIT 2
Clock2 S PWM2 Phase2
Q
R
L2
I L2
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
Crs2
Vcrs2
gm
SLAVE CIRCUIT 3
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal to
g m V o , where g m is a gain factor. C rm voltage V crm is a sawtooth
waveform traversing between the VW and COMP voltages. It resets
to VW when it hits COMP, and generates a one-shot master clock
signal. A phase sequencer distributes the master clock signal to
Crs3
VW
Vcrs3
Clock3
gm
S
R
Q
PWM3 Phase3
L3
I L3
the slave circuits. If VR1 is in 4-phase mode, the master clock
signal will be distributed to the four phases, and the Clock1~4
signals will be 90° out-of-phase. If VR1 is in 3-phase mode, the
master clock signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If VR1 is in 2-phase
mode, the master clock signal will be distributed to Phases 1 and 2,
and the Clock1 and Clock2 signals will be 180° out-of-phase. If
VR1 is in 1-phase mode, the master clock signal will be distributed
to Phase 1 only and be the Clock1 signal.
11
FIGURE 3. R3 MODULATOR CIRCUIT
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
voltage V Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C rs .
FN6898.1
September 5, 2013
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