参数资料
型号: ISL6410AIUZ-T5K
厂商: Intersil
文件页数: 6/13页
文件大小: 0K
描述: IC REG BUCK SYNC 0.6A 10MSOP
标准包装: 5,000
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.2V,1.8V,3.3V
输入电压: 3 V ~ 3.6 V
PWM 型: 电流模式
频率 - 开关: 750kHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
ISL6410, ISL6410A
Electrical Specifications
Recommended operating conditions unless otherwise noted. V IN = 3.3V ±10% (ISL6410) or 5V ±10%
(ISL6410A), T A = 25°C (Note 6). (Continued)
Efficiency
Efficiency
Soft-Start Time
PARAMETER
TEST CONDITIONS
I OUT = 200mA, V IN = 5.0V, V O = 3.3V (ISL6410A)
I OUT = 600mA, V IN = 5.0V, V O = 3.3V (ISL6410A)
4096 Clock Cycles @ 750kHz
MIN
-
-
-
TYP
93
91
5.5
MAX
-
-
-
UNITS
%
%
ms
OSCILLATOR
Oscillator Frequency
620
750
860
kHz
Frequency Synchronization Range (f SYNC )
SYNC High Level Input Voltage
SYNC Low Level Input Voltage
Sync Input Leakage Current
Duty Cycle of External Clock Signal (Note 7)
Clock signal on SYNC pin
As % of VIN
As % of VIN
SYNC = GND or V IN
500
70
-
-1
20
-
-
-
-
-
1000
-
30
1
60
kHz
%
%
μ A
%
PGOOD (ISL6410 interfaces to 3.3V Logic, ISL6410A interfaces to 5.0V Logic)
Rising Threshold
Falling Threshold
Rising/Falling Hysteresis
1mA minimum source/sink
+5.0
-10.5
-
8.0
-8.0
1
+10.5
-5.0
-
%
%
%
ENABLE
EN High Level Input Voltage
EN Low Level Input Voltage
EN Input Leakage Current
As % of VIN
As % of VIN
EN = GND or V IN
70
-
-1
-
-
-
30
1
%
%
μ A
OVERVOLTAGE
Overvoltage Threshold
27
30
33
%
RESET BLOCK SPECIFICATIONS
RESET (reset released)
RESET (reset asserted)
RESET Rising Threshold
RESET Falling Threshold
RESET (reset released)
RESET (reset asserted)
RESET Rising Threshold
RESET Falling Threshold
RESET Threshold Hysteresis
RESET Threshold Hysteresis
RESET Active Timeout Period (Note 8)
ISL6410, ISOURCE = 500μA, VIN = 2.90V
ISL6410, ISINK = 1.2mA, VIN = 2.50V
ISL6410
ISL6410
ISL6410A, ISOURCE = 800μA, VIN = 4.70V
ISL6410A, ISINK = 3.2mA, VIN = 4.10V
ISL6410A
ISL6410A
ISL6410
ISL6410A
CT = 0.01mF
0.8V IN
-
2.74
2.72
0.8V IN
-
4.5
4.47
-
-
-
-
-
2.78
2.77
-
-
4.58
4.55
20
30
25
-
0.3
2.81
2.79
-
0.4
4.64
4.61
-
-
-
V
V
V
V
V
V
V
V
mV
mV
ms
V SET
V SET High Level Input
V SET Low Level Input
V SET Open Level Input
V IN -0.4V
-
-
-
-
V IN /2
-
0.4
-
V
V
V
NOTES:
6. Specifications at -40°C and +85°C are guaranteed by design, not production tested.
7. Guaranteed by design, not production tested.
8. The RESET Timeout period is linear with C T at a slope of 2.5ms/nF, thus a 10nF capacitor provides for 25ms.
6
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