参数资料
型号: ISL6420AIAZ-TK
厂商: Intersil
文件页数: 17/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20-QSOP
标准包装: 1
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SSOP(0.154",3.90mm 宽)
包装: 标准包装
其它名称: ISL6420AIAZ-TKDKR
ISL6420A
VIN
Compensation Break Frequency Equations
F Z1 = ----------------------------------
OSC
PWM
COMPARATOR
DRIVER
L O
V OUT
1
2 π ? R 2 ? C1
(EQ. 6)
-
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
-
F Z2 = ------------------------------------------------------
F P2 = ----------------------------------
Δ V OSC
+
Z FB
V E/A
+
ERROR
AMP
DRIVER
Z IN
REFERENCE
PHASE
C O
ESR
(PARASITIC)
1
C1 ? C2
? C1 + C2 ?
1
2 π ? ( R1 + R3 ) ? C3
1
2 π ? R3 ? C3
(EQ. 7)
(EQ. 8)
(EQ. 9)
1. Pick Gain (R2/R1) for desired converter bandwidth
DETAILED COMPENSATION COMPONENTS
2. Place 1 ST Zero Below Filter’s Double Pole
C 1
C 2
R 2
Z FB
C 3
Z IN
R 3
V OUT
(~75% F LC )
3. Place 2 ND Zero at Filter’s Double Pole
4. Place 1 ST Pole at the ESR Zero
5. Place 2 ND Pole at Half the Switching Frequency
COMP
-
FB
R 1
6. Check Gain against Error Amplifier’s Open-Loop
Gain
7. Estimate Phase Margin - Repeat if Necessary
+
ISL6420A
REF
R 4
Figure 18 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator
Gain has a high gain peak due to the high Q factor of
the output filter and is not shown in Figure 18. Using
V OUT = V REF × ? 1 + ------ 1 - ?
F LC = ---------------------------------------
2 π ? L O ? C O
? R ?
? R 4 ?
FIGURE 17. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1
(EQ. 4)
the previously mentioned guidelines should give a
Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at
F P2 with the capabilities of the error amplifier. The Loop
Gain is constructed on the log-log graph of Figure 18
by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
F ESR = ---------------------------------------------
1
2 π ? ( ESR ? C O )
(EQ. 5)
100
80
F Z1 F Z2
F P1
F P2
The compensation network consists of the error
amplifier (internal to the ISL6420A) and the
impedance networks Z IN and Z FB . The goal of the
compensation network is to provide a closed loop
transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase
margin is the difference between the closed loop phase
at f 0dB and 180°. The following equations relate the
compensation network’s poles, zeros and gain to the
components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in Figure 17.
Use the following guidelines for locating the poles and
60
40
20
0
-20
-40
-60
20LOG
(R 2 /R 1 )
MODULATOR
GAIN
10 100 1k
F LC
10k
OPEN LOOP
ERROR AMP GAIN
20LOG
(VIN/ Δ V OSC )
COMPENSATION
GAIN
CLOSED LOOP
GAIN
F ESR
100k 1M 10M
zeros of the compensation network.
17
FREQUENCY (Hz)
FIGURE 18. ASYMPTOTIC BODE PLOT OF CONVERTER
GAIN
FN9169.4
December 4, 2009
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