参数资料
| 型号： | ISL6420BIRZ |
| 厂商： | Intersil |
| 文件页数： | 16/21页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 100% |
| 电源电压： | 4.5 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6420B
V IN = 12V, V OUT = 3.3V at 25mA LOAD
ISL6420B
VIN
UGATE
PHASE
Q1
L O
V OUT
LGATE
Q2
D2
C IN
C O
GND
RETURN
FIGURE 15. PRINTED CIRCUIT BOARD POWER AND
FIGURE 14. PREBIASED OUTPUT AT 25mA LOAD
Application Guidelines
GROUND PLANES OR ISLANDS
Layout Considerations
As in any high frequency switching converter, layout is
very important. Switching current from one power
device to another can generate voltage transients
across the impedances of the interconnecting bond
wires and circuit traces. These interconnecting
impedances should be minimized by using wide, short
printed circuit traces. The critical components should
be located as close together as possible using ground
plane construction or single point grounding.
ENSS
C SS
ISL6420B
GND
BOOT
C BOOT
PHASE
+5V
V CC
D 1
C VCC
+VIN
Q 1 L
Q 2
O
C O
V OUT
Figure 15 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should
be part of ground or power plane in a printed circuit
board. The components shown in Figure 15 should be
located as close together as possible. Please note that
the capacitors C IN and C O each represent numerous
physical capacitors. Locate the ISL6420B within 3
inches of the MOSFETs, Q 1 and Q 2 . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6420B must be sized to handle up to 1A peak
current.
Figure 16 shows the circuit traces that require
additional layout consideration. Use single point and
ground plane construction for the circuits shown.
Minimize any leakage current paths on the SS PIN and
locate the capacitor, C ss close to the SS pin because
the internal current source is only 10μA. Provide local
V CC decoupling between VCC and GND pins. Locate
the capacitor, C BOOT as close as practical to the BOOT
and PHASE pins.
16
FIGURE 16. PRINTED CIRCUIT BOARD SMALL
SIGNAL LAYOUT GUIDELINES
Feedback Compensation
Figure 17 highlights the voltage-mode control loop for
a synchronous-rectified buck converter. The output
voltage (V OUT ) is regulated to the Reference voltage
level. The error amplifier (Error Amp) output (V E/A ) is
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of VIN at the PHASE node. The PWM wave
is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal
transfer function of V OUT /V E/A . This function is
dominated by a DC Gain and the output filter (L O and
C O ), with a double pole break frequency at F LC and a
zero at F ESR . The DC Gain of the modulator is simply
the input voltage (VIN) divided by the peak-to-peak
oscillator voltage Δ V OSC .
FN6901.1
December 4, 2009
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| ISL6420BMAEP-TK | 制造商:Intersil Corporation 功能描述:VOLT MODE PWM CNTRLR 20QSOP W - Tape and Reel |
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