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| 型号： | ISL6421AERZ |
| 厂商： | Intersil |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR VOLT REG SGL I2C 32QFN |
| 标准包装： | 60 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13 V ~ 18 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
ISL6421A
Byte Format
TABLE 2. INTERFACE PROTOCOL
Every byte put on the SDA line must be 8-bits long. The
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
TABLE 3. SYSTEM REGISTER 1 (SR1)
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
R, W
SR1
R, W
DCL
R, W
X
R, W
ENT
R, W
LLC
R, W
VSEL
R, W
EN
R
OLF
The master (microprocessor) puts a resistive HIGH level on
TABLE 4. SYSTEM REGISTER 2 (SR2)
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull the SDA line
down (LOW) during the acknowledge clock pulse, so that the
R, W
SR2
R, W
X
R, W
X
R, W
X
R, W
X
R, W
X
R
OTF
R
X
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421A will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
SCL
System Register Format
? R, W = Read and Write bit
? R = Read-only bit
All bits reset to 0 at Power-On
Transmitted Data ( I 2 C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1/SR2)
of the ISL6421A via I 2 C bus. These will be written by the
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.
1
2
8
9
TABLE 5. SYSTEM REGISTER (SR1 AND SR2)
SDA
CONFIGURATION
MSB
SR DCL - ENT LLC VSEL EN OLF
FUNCTION
START
ACKNOWLEDGE
FROM SLAVE
0
0
X
X
0
0
0
0
1
1
SR1 is selected
Vout1 = 13V,
FIGURE 3. ACKNOWLEDGE ON THE I 2 C BUS
Vboost1 = 13V + Vdrop
0
X
0
1
1
Vout1 = 18V,
Transmission Without Acknowledge
Vboost1 = 18V + Vdrop
Avoiding detection of the acknowledgement, the
0
X
1
0
1
Vout1 = 14V,
microprocessor can use a simpler transmission; it waits one
Vboost1 = 14V + Vdrop
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
0
0
X
X
0
1
1
1
1
Vout1 = 19V,
Vboost1 = 19V + Vdrop
22kHz tone is controlled
decreases the noise immunity.
by the DSQIN pin input
ISL6421A Software Description
0
X
1
1
22kHz tone is ON,
DSQIN pin input is
Interface Protocol
disabled
The interface protocol is comprised of the following, as
shown below in Table 2:
? A start condition (S)
0
0
1
0
X
X
1
1
Dynamic current limit
NOT selected
Dynamic current limit
selected
? A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I 2 C slave
address for the ISL6421A is 0001 00XX)
? A sequence of data (1 byte + Acknowledge)
? A stop condition (P)
0
SR
1
X
-
X
X
-
X
X
-
X
X
-
X
X
-
X
0
OTF
X
PWM and Linear for
channel 1 disabled
- FUNCTION
X SR2 is selected; to read
OTF flag.
8
FN9167.3
March 9, 2006
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