参数资料
型号: ISL6422EVEZ
厂商: Intersil
文件页数: 12/19页
文件大小: 0K
描述: IC VREG DUAL LNB W/I2C 38EPTSSOP
标准包装: 1,000
应用: 转换器,卫星信号接收机顶盒设计
输入电压: 8 V ~ 14 V
输出数: 2
输出电压: 13.3 V ~ 18.3 V,14.3 V ~ 19.3 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 38-TFSOP (0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 38-TSSOP 裸露焊盘
包装: 管件
ISL6422
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
The ISL6422 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
SCL
can change only when the clock signal on the SCL line is
LOW. Refer to Figure 4.
1
2
8
9
SDA
SDA
START
MSB
ACKNOWLEDGE
FROM SLAVE
SCL
DATA LINE
CHANGE
FIGURE 6. ACKNOWLEDGE ON THE I 2 C BUS
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 4. DATA VALIDITY
START and STOP Conditions
As shown in Figure 5, the START condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
SDA
SCL
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock pulse without checking the slave acknowledging and
sends the new data. Although, this approach is less
protected from error and decreases the noise immunity.
ISL6422 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown in Table 2:
? Start condition (S)
? Chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I 2 C slave
S
START
CONDITION
P
STOP
CONDITION
address for the ISL6422 is 0001 00XX)
? Sequence of data (1 byte + Acknowledge)
FIGURE 5. START AND STOP WAVEFORMS
Byte Format
? Stop condition (P)
TABLE 2. INTERFACE PROTOCOL
Every byte put on the SDA line must be eight bits long. The
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (see
System Register Format
? R, W = Read and Write bit
? R = Read-only bit
? X = Unused
All bits reset to 0 at Power-On
TABLE 3. STATUS REGISTER 1 (SR1)
Figure 6). The peripheral that acknowledges has to pull
R, W
R, W
R, W
R
R
R
R
R
down (LOW) the SDA line during the acknowledge clock
SR1H
SR1M
SR1L
OTF
CABF1 OUVF1 OLF1
BCF1
pulse, so that the SDA line is stable LOW during this clock
pulse. (Set-up and hold times must also be taken into
TABLE 4. TONE REGISTER 2 (SR2)
account).
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
The peripheral which has been addressed has to generate
SR2H
SR2M
SR2L
ENT1
MSEL1 TTH1
X
X
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
TABLE 5. COMMAND REGISTER 3 (SR3)
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
12
SR3H SR3M SR3L
DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L
X
FN9190.2
August 10, 2007
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