参数资料
| 型号： | ISL6423EVEZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC VREG SGL LNB W/I2C 28-HTSSOP |
| 标准包装： | 2,500 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6423
Typical Performance Curves
0.90
0.80
0.70
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
I OUT _max
0.60
0.50
0.40
0.30
0.20
0.10
I OUT _max
0.00
0
20
40
60
80
0.00
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 2. OUTPUT CURRENT DERATING (HTSSOP)
Functional Pin Description
TEMPERATURE (°C)
FIGURE 3. OUTPUT CURRENT DERATING (4x4 QFN)
SYMBOL
SDA
SCL
VSW
PGND
CS
SGND
TCAP
BYPASS
TXT
VCC
GATE
VO
FUNCTION
Bidirectional data from/to I 2 C bus.
Clock from I 2 C bus.
Input of the linear post-regulator.
Dedicated ground for the output gate driver of respective PWM.
Current sense input; connect the sense resistor Rsc at this pin for desired peak overcurrent value for the boost FET. The
set peak limit is effective in the static mode current limit only (i.e., DCL = HIGH).
Small signal ground for the IC.
Capacitor for setting rise and fall time of the output voltage. Typical value is 0.1μF.
Bypass capacitor for internal 5V.
TXT is the Tone Transmit signal input used to change the Tone Decoder Threshold from TXT = 0, 200mV maximum during
Receive to TXT = 1, 400mV minimum during transmit.
Main power supply to the chip.
This output drives the boost FET gate. The output is held low when VCC is below the UVLO threshold.
Output voltage for the LNB is available at VO pin.
ADDR0 and ADDR1 Logic combination at the ADDR0 and 1 can select four different chip select addresses.
EXTM
FLT
CPVOUT, CPSWIN
CPSWOUT
SELVTOP
TDIN, TDOUT
This pin can be used in two ways:
1) As an input for externally modulated Diseqc tone signal which is transferred to the symmetrically onto Vout
2) Alternatively apply a Diseqc modulation envelope which modulates an internal tone and then transfers it symmetrically
onto Vout.
This is an open drain output from the controller. when the flt goes low it indicates that an over temperature, over load fault,
back current fault, UVLO, or an I 2 C reset condition has occurred. The processor should then look at the I 2 C register to get
the actual cause of the error. A high on the FLT indicates that the device is functioning normally.
A 47n charge pump decoupling capacitor is to be connected to CPVOUT. Connect a 1.5n capacitor between CPSWIN and
CPSWOUT.
When this pin is low the Vout is in the 13V/14V range selected by the I 2 C bit VBOT.
When this pin is high the 18V/19V range selected by the I 2 C bit VTOP. The Voltage select pin enable VSPEN I 2 C bit must
be set low for the SELVTOP pins to be active. Setting VSPEN high disables this pins and voltage selection will be done
using the I 2 C bits VBOT and VTOP only.
TDIN is the tone decoder input and TDOUT is the tone detector output. TDOUT is an open drain output.
8
FN9191.2
December 5, 2008
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