参数资料
| 型号： | ISL6444CA-T |
| 厂商： | Intersil |
| 文件页数： | 10/19页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR 28-QSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，DDR |
| 输入电压： | 4.5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5.5 V |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 28-SSOP/QSOP |
| 包装： | 带卷 (TR) |
ISL6444
is usually higher compared to the load level at which
transition into hysteretic mode had occurred.
VOUT pin and Forced Continuous Conduction Mode (FCCM)
The error amplifier that provides control over the converter
Figure 5 shows a Type 2 amplifier and its response along
with the responses of the current mode modulator and the
converter. The Type 2 amplifier, in addition to the pole at
origin, has a zero-pole pair that causes a flat gain region at
frequencies in between the zero and the pole.;
1
F Z = = 6kHz
2 π ? R 2 ? C 1
F P = ------------------------------- = 600kHz
during CCM mode is excluded from the regulation loop in the
hysteretic mode. Due to that, its output voltage eventually
runs away from the operation point that is normally related to
the desired output voltage. When the converter transitions
from hysteretic mode of operation into CCM, the output
-------------------------------
1
2 π ? R 1 ? C 2
(EQ. 8)
(EQ. 9)
voltage transient can occur as it takes some time for the
error amplifier to catch-up with regulation.
To reduce undesirable effects of the error amplifier run away
during mode change, the exact value of the output voltage is
provided to the internal circuit via the VOUT pin, Figure 2.
In case the hysteretic mode of operation is not required, the
controller can be put in a forced continuous conduction
This region is also associated with phase ‘bump’ or
reduced phase shift. The amount of phase shift reduction
depends on how wide the region of flat gain is and has a
maximum value of 90°. To further simplify the converter
compensation, the modulator gain is kept independent of
the input voltage variation by providing feed-forward of V IN
to the oscillator ramp.
C2
mode (FCCM) of operation. That can be accomplished by
R2
C1
connecting the VOUT pin to ground, which disables the
mode control circuit.
Converter
R1
Such dual function of the VOUT pin enhances applicability of
the controller and allows for lower pin count.
EA
Type 2 EA
Feedback Loop Compensation
To reduce the number of external components and remove
the burden of determining compensation components from a
system designer, both PWM controllers have internally
compensated error amplifiers. To make internal compensation
possible several design measures where taken.
G M = 18dB
Modulator
F PO
F Z
G EA = 14dB
F C
F P
First, the ramp signal applied to the PWM comparator is
proportional to the input voltage provided via the VIN pin.
This keeps the modulator gain constant when the input
voltage varies. The second, the load current proportional
signal is derived from the voltage drop across the lower
MOSFET during the PWM time interval and is added to the
amplified error signal on the comparator input. This
effectively creates an internal current control loop. The
resistor connected to the ISEN pin sets the gain in the
current feedback loop. Equation 6 estimates the required
value of the current sense resistor depending on the
maximum load current and the value of the MOSFET’s
FIGURE 5. FEEDBACK LOOP COMPENSATION
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
I MAX ? r DS ( ON )
r DS(ON) .
75 μ A
R CS = ----------------------------------------- – 100 Ω
(EQ. 6)
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
F PO = ---------------------------------
2 π ? R O ? C O
Due to implemented current feedback, the modulator has a
single pole response with -1 slope at a frequency
determined by the load in Equation 7.
where: Ro -- is load resistance and Co -- is load capacitance.
1
(EQ. 7)
For this type of modulator, a Type 2 compensation circuit is
usually sufficient.
10
ESR zero placed within 10kHz...50kHz range gives some
additional phase ‘boost’. Some phase boost can also be
achieved by connecting capacitor C z in parallel with the
upper resistor R1 of the divider that sets the output voltage
value, as shown in Figure 2.
FN9069.3
April 12, 2007
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相关代理商/技术参数 |
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| ISL6444CAZ | 功能描述:IC CONTROLLER DDR 28-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6444CAZT | 制造商:Intersil Corporation 功能描述: |
| ISL6444CAZ-T | 功能描述:IC CONTROLLER DDR 28-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6445EVAL3Z | 功能描述:EVALUATION BOARD FOR ISL6445 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6445IAZ | 功能描述:IC REG CTRLR BUCK PWM CM 24-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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