参数资料
型号: ISL6455AIRZ-T5KS2698
厂商: Intersil
文件页数: 6/12页
文件大小: 0K
描述: IC REG TRPL SYNC DUAL LDO 24-QFN
标准包装: 5,000
应用: 转换器,FPGAs
输入电压: 4.2 V ~ 5.5 V
输出数: 3
输出电压: 0.8 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 带卷 (TR)
ISL6455, ISL6455A
Electrical Specifications
Recommended operating conditions unless otherwise noted. V IN = V IN _LDO = PV CC = 3.3V for ISL6455 and
5.0V for the ISL6455A, Compensation Capacitors = 33nF for LDO1 and LDO2. T A = -40°C to 85° (Note 2), typical
values are at T A = 25°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE (EN and (EN_LDO)
EN High Level Input Voltage
EN Low Level Input Voltage
As % of VIN
As % of VIN
70
-
-
-
-
30
%
%
RESET BLOCK SPECIFICATIONS
RESET (reset released)
ISL6455, ISOURCE = 500 μ A, VIN = 2.90V
0.8 x
-
-
V
V CC
RESET (reset asserted)
RESET Rising Threshold
RESET Falling Threshold
RESET (reset released)
ISL6455, ISINK = 1.2mA, VIN = 2.50V
ISL6455
ISL6455
ISL6455A, ISOURCE = 800 μ A, VIN = 4.70V
-
2.71
2.69
0.8 x
-
2.77
2.75
-
0.3
2.84
2.81
-
V
V
V
V
V CC
RESET (reset asserted)
RESET Rising Threshold
RESET Falling Threshold
RESET Threshold Hysteresis
RESET Threshold Hysteresis
RESET Active Timeout Period (Note 5)
ISL6455A, ISINK = 3.2mA, VIN = 4.10V
ISL6455A
ISL6455A
ISL6455
ISL6455A
C T = 0.01 μ F
-
4.19
4.16
-
-
-
-
4.27
4.24
20
30
25
0.4
4.35
4.32
-
-
-
V
V
V
mV
mV
ms
POWER GOOD (PG_LDO)
Minimum Input Voltage for Valid PG_LDO
-
1.2
-
V
PGOOD Threshold (Rising)
PGOOD Threshold (Falling)
PGOOD Output Voltage Low
PGOOD Output Leakage Current
FB_LDO vs 1.184V Vref
I OL = 1.2mA
PG_LDO = GND or VIN
+11
-17
-
-
+15
-15
-
0.01
+17
-11
0.4
0.1
%
%
V
μ A
PWM OUTPUT OVERVOLTAGE
Overvoltage Threshold
FB_PWM vs 0.45V Vref
28
31
34
%
NOTES:
3. Specifications at -40°C and +85°C are guaranteed by 25°C test with margin limits.
4. This is the V IN current consumed when the device is active but not switching. Does not include gate drive current.
5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01 μ F) the RESET time is 25ms; at 1000nF (0.1 μ F) the
RESET time would be 250ms.
7. Guaranteed by design, not production tested.
8. Add the external feedback resistor mismatch error to get initial V OUT accuracy.
6
FN9196.0
December 21, 2005
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