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参数资料
| 型号： | ISL6504ACRZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CTRLR/MONITR 20QFN |
| 标准包装： | 4,000 |
| 应用： | 电源控制器/监控器 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 17mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
ISL6504, ISL6504A
Soft-Start into Sleep States (S3, S4/S5)
The 5V SB POR function initiates the soft-start sequence. An
internal 10 μ A current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start
sequence for the typical application start-up into a sleep
state. At time T0 5V SB (bias) is applied to the circuit. At time
T1, the 5V SB surpasses POR level. An internal fast charge
0V
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
VOUT4 (5VDUAL)
(1V/DIV)
circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10 μ A current source continues
the charging.
5VSB
(1V/DIV)
0V
VOUT3 (3.3VDUAL/3.3VSB)
OUTPUT
VOLTAGES
VOUT1 (1.5VSB)
VOUT2
(1.2VVID)
SOFT-START
T0
T1 T2
T3
T4
T5
0V
(1V/DIV)
VOUT3 (3.3VDUAL/3.3VSB)
OUTPUT
VOUT4 (5VDUAL) IF S3
TIME
FIGURE 8. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6054A
The soft-start capacitor voltage reaches approximately
1.25V at time T2, at which point the 3.3V DUAL /3.3V SB and
1.5V SB error amplifiers’ reference inputs start their
transition, resulting in the output voltages ramping up
proportionally. The ramp-up continues until time T3 when the
two voltages reach the set value. As the soft-start capacitor
voltage reaches approximately 2.75V, the undervoltage
0V
VOLTAGES
(1V/DIV)
VOUT1 (1.5VSB)
VOUT2
(1.2VVID)
monitoring circuit of this output is activated and the soft-start
capacitor is quickly discharged to approximately 1.25V.
Following the 3ms (typical) time-out between T3 and T4, the
soft-start capacitor commences a second ramp-up designed
VOUT4 (5VDUAL) if S5
to smoothly bring up the remainder of the voltages required
T0
T1 T2
T3
TIME
T4
T5
by the system. At time T5, voltages are within regulation
limits, and as the SS voltage reaches 2.75V, all the
FIGURE 7. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6504
9
remaining UV monitors are activated and the SS capacitor is
quickly discharged to 1.25V, where it remains until the next
transition. As the 1.2V VID output is only active while in an
active state, it does not come up, but rather waits until the
main ATX outputs come up within regulation limits.
Soft-Start into Active States (S0, S1)
If both S3 and S5 are logic high at the time the 5V SB is
applied, the ISL6504/A will assume active state wake-up and
keep off the required outputs until some time (typically
25ms) after the monitored main ATX output (3.3V) exceeds
the set threshold. This time-out feature is necessary in order
to ensure the main ATX outputs are stabilized. The time-out
also assures smooth transitions from sleep into active when
sleep states are being supported. 3.3V DUAL /3.3V SB and
1.5V SB outputs will come up right after bias voltage
surpasses POR level.
FN9062.2
April 13, 2004
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