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参数资料
| 型号： | ISL6504ACRZ |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CTRLR/MONITR 20QFN |
| 标准包装： | 50 |
| 应用： | 电源控制器/监控器 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 17mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（6x6） |
| 包装： | 管件 |
ISL6504, ISL6504A
I COUT = ------------------------------ × Σ ( C OUT × V OUT ) , where
excessive amounts of current from the 5V SB output of the
ATX can lead to voltage collapse and induce a pattern of
consecutive restarts with unknown effects on the system’s
behavior or health.
The built-in soft-start circuitry allows tight control of the slew-
up speed of the output voltages controlled by the ISL6504,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
I SS
C SS × V BG
80
70
60
50
40
30
20
10
I SS - soft-start current (typically 10 μ A)
0
0
1
2
3
4
5
6
7
8
9
10
C SS - soft-start capacitor
V BG - bandgap voltage (typically 1.26V)
Σ ( C OUT x V OUT ) - sum of the products between the
capacitance and the voltage of an output (total charge
delivered to all outputs)
Due to the various system timing events and their
interaction, it is recommended that the soft-start interval not
be set to exceed 30ms. For most applications, a 0.1 μ F
capacitor is recommended.
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, all the ISL6504/A
outputs can be shut down by pulling the SS pin below the
specified shutdown level (typically 0.8V) with an open drain
or open collector device capable of sinking a minimum of
2mA. Pulling the SS pin low effectively shuts down all the
pass elements. Upon release of the SS pin, the ISL6504
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control pins
status.
VID_PG Delay
During power-up and initial soft-start, the VID_PG and
VID_CT pins are held low. As the 1V2VID output exceeds its
rising power-good threshold, the capacitor connected at the
VID_CT pin starts to charge up through the internal 10 μ A
current source. As the voltage on this capacitor exceeds
1.25V, the open-collector VID_PG pin is released and VID
POWER GOOD status is thus reported.
The value of the VID_CT capacitor to be used to obtain a
given VID_PG delay can be determined from the graph in
Figure 10. For extended delays exceeding the range of the
graph, use the following formula:
VID_PG Delay (ms)
FIGURE 10. VID_PG DELAY DEPENDENCE ON VID_CT
CAPACITOR
Layout Considerations
The typical application employing an ISL6504/A is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
controller chip and processor, but not excessively far from
the 3.3V DUAL island or the I/O circuitry. Ensure the 1V5SB,
1V2VID, 3V3, and 3V3DL connections are properly sized to
carry 100mA without exhibiting significant resistive losses at
the load end. Similarly, the input bias supply (5V SB ) can
carry a significant level of current - for best results, ensure it
is connected to its respective source through an adequately
sized trace. The pass transistors should be placed on pads
capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
high-frequency decoupling capacitors should be placed as
close as possible to the load they are decoupling; the ones
decoupling the controller close to the controller pins, the
ones decoupling the load close to the load connector or the
load itself (if embedded). Even though bulk capacitance
(aluminum electrolytics or tantalum capacitors) placement is
not as critical as the high-frequency capacitor placement,
t DELAY
C = --------------------
125000
, where
having these capacitors close to the load they serve is
preferable.
t DELAY - desired delay time (s)
C - VID_CT capacitor to obtain desired delay time (F)
11
The critical small signal components include the soft-start
capacitor, C SS , as well as all the high-frequency decoupling
capacitors. Locate these components close to the respective
FN9062.2
April 13, 2004
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| ISL6504CBN | 功能描述:IC MULTIPLE POWER CTRLR 16-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
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