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| 型号： | ISL6506CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CTRLR/MONITR 8SOIC |
| 标准包装： | 2,500 |
| 应用： | 电源控制器/监控器 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 3.6mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
ISL6506, ISL6506A, ISL6506B
to a high impedance state, which allows the 12V rail to
enhance the two N-MOSFETs (Q 1 and Q 3 ) that connect the
ATX rails to the 3.3V DUAL and 5V DUAL rails. The 5VDLSB
pin is actively pulled high, which will turn the P-MOSFET
12VATX
5VSB
CIN
(Q 2 ) off. Finally, the internal LDO which regulates the
3.3V DUAL rail in sleep states is put in standby mode.
Internal Linear Regulator Undervoltage Protection
+3.3VIN
C 5VSB
VCC
5VDLSB
Q3
5VDUAL
The undervoltage protection on the internal linear regulator
is only active during sleep states and after the initial soft-start
ISL6506,
C 5V
C HF5V
ramp of the 3.3V linear regulator. The undervoltage trip point
is set at 25% below nominal, or 2.475V.
When an undervoltage is detected, the 3.3V linear regulator
is disabled. One soft-start interval later, the 3.3V linear
regulator is retried with a soft-start ramp. If the linear
regulator is retried 3 times and a fourth undervoltage is
Q2
3V3DUAL
C HF3V
C 3V
ISL6506A,
ISL6506B
DLA
3V3AUX
GND
EPAD
Q4
5VATX
detected, then the 3.3V linear regulator is disabled and can
only be reset through a POR reset.
Internal Linear Regulator Overcurrent Protection
When an overcurrent condition is detected, the gate voltage
to the internal NMOS pass element is reduced, which
causes the output voltage of the linear regulator to be
reduced. When the output voltage is reduced to the
undervoltage trip point, the undervoltage protection is
initiated and the output will shutdown.
Layout Considerations
The typical application employing an ISL6506 is a fairly
straight forward implementation. Like with any other linear
regulator, attention has to be paid to the few potentially
sensitive small signal components, such as those connected
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, not excessively far
from the 3.3V DUAL island or the I/O circuitry. Ensure the
3V3AUX connection is properly sized to carry 1A without
exhibiting significant resistive losses at the load end.
Similarly, the input bias supply (5V SB ) carries a similar level
of current (for best results, ensure it is connected to its
respective source through an adequately sized trace and is
properly decoupled). The pass transistors should be placed
on pads capable of heatsinking matching the device’s power
dissipation. Where applicable, multiple via connections to a
large internal plane can significantly lower localized device
temperature rise.
Placement of the decoupling and bulk capacitors should
reflect their purpose. As such, the high-frequency
decoupling capacitors should be placed as close as possible
to the load they are decoupling; the ones decoupling the
controller close to the controller pins, the ones decoupling
the load close to the load connector or the load itself (if
embedded). Even though bulk capacitance (aluminum
electrolytics or tantalum capacitors) placement is not as
6
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD ISLANDS
critical as the high-frequency capacitor placement, having
these capacitors close to the load they serve is preferable.
Locate all small signal components close to the respective
pins of the control IC, and connect them to ground, if
applicable, through a via placed close to the ground pad.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections to most of the components
in the circuit. Note that the individual capacitors shown each
could represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections through vias placed as close
to the component terminal as possible. The EPAD should be
tied to the ground plane with three to five vias for good
thermal management. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
Component Selection Guidelines
Output Capacitors Selection
The output capacitors should be selected to allow the output
voltage to meet the dynamic regulation requirements of
active state operation (S0/S1). The load transient for the
various microprocessor system’s components may require
high quality capacitors to supply the high slew rate (di/dt)
FN9141.6
September 12, 2013
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| ISL6520ACB | 功能描述:IC REG CTRLR BUCK PWM VM 8-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
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