参数资料
型号: ISL6520ACBZA-T
厂商: Intersil
文件页数: 7/12页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
标准包装: 2,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 340kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
ISL6520A
ISL6520A
V IN
pulse-width modulated (PWM) wave with an amplitude of
V IN at the PHASE node. The PWM wave is smoothed by the
output filter (L O and C O ).
UGATE
PHASE
Q 1
L O
V OUT
OSC
PWM
COMPARATOR
DRIVER
V IN
L O
V OUT
+
LGATE
Q 2
C IN
C O
Δ V OSC
-
DRIVER
PHASE
C O
ESR
RETURN
V E/A
Z FB
(PARASITIC)
+
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 3 shows the critical power components of the converter.
-
ERROR
AMP
Z IN
REFERENCE
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
DETAILED COMPENSATION COMPONENTS
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors C IN and C O may each
C 1
C 2
R 2
Z FB
C 3
Z IN
R 3
V OUT
represent numerous physical capacitors. Locate the ISL6520A
within 3 inches of the MOSFETs, Q 1 and Q 2 . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520A must be sized to handle up to 1A peak current.
Figure 4 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
COMP
-
+
ISL6520A
REFERENCE
FB
R 1
current paths on the COMP/OCSET pin and locate the
resistor, R OSCET close to the COMP/OCSET pin because
the internal current source is only 20μA. Provide local V CC
decoupling between VCC and GND pins. Locate the
capacitor, C BOOT as close as practical to the BOOT and
PHASE pins. All components used for feedback
compensation should be located as close to the IC a
practical.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
F LC = -------------------------------------------
F ESR = --------------------------------------------
+5V
ISL6520A
BOOT
C BOOT
PHASE
VCC
+5V
D 1
+V IN
Q 1
Q 2
L O
C O
V OUT
Modulator Break Frequency Equations
1 1
2 π x LO x CO 2 π x ESR x C O
(EQ. 4)
The compensation network consists of the error amplifier
COMP/OCSET
GND
C VCC
(internal to the ISL6520A) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V E/A ) is compared with
the oscillator (OSC) triangular wave to provide a
7
is the difference between the closed loop phase at f 0dB and
180 degrees. The following equations relate the
compensation network’s poles, zeros and gain to the
components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in Figure 7. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter ’s Double Pole.
FN9016.6
December 10, 2009
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