参数资料
型号: ISL6520BCB
厂商: Intersil
文件页数: 4/10页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 8-SOIC
标准包装: 98
PWM 型: 电压模式
输出数: 1
频率 - 最大: 340kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
ISL6520B
Functional Pin Description
VCC
This pin provides the bias supply for the ISL6520B, as well
as the lower MOSFET’s gate. Connect a well-decoupled 5V
supply to this pin.
FB
This pin is the inverting input of the internal error amplifier.
Use this pin, in combination with the COMP/SD pin, to
compensate the voltage-control feedback loop of the
converter.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source.
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
COMP/SD
This pin is the output of the error amplifier. Use this pin, in
combination with the FB pin, to compensate the voltage-
Functional Description
Initialization
The ISL6520B automatically initializes upon receipt of power.
The Power-On Reset (POR) function continually monitors the
bias voltage at the VCC pin. The POR function initiates the soft
start operation.
Soft Start
The ISL6520B is held in reset with both UGATE and LGATE
driven to ground until the POR threshold on VCC has been
reached and the COMP/SD pin has been pulled above 0.8V. If
COMP is not actively pulled high following POR the internal
20 μ A current sink will hold COMP/SD low and the device will
remain in reset. COMP/SD can either be statically tied to VCC
through a pullup resistor or driven high through a resistor to
terminate reset. The recommended range of resistor values to
use as the pullup resistor is between 50k Ω and 100k Ω .
Following reset the ISL6520B provides a 1024 clock cycle
settling period (~3.4ms) prior to initiating softstart. At the
conclusion of the settling period the COMP/SD pin is driven
to 0.8V for 24 clock cycles (~75 μ s) to discharge the
compensation network. Soft start of the regulated output is
generated by imposing an internal offset on the FB pin which
ramps down from 0.8V to 0V over the next 2048 clock cycles
(~6.8ms). Total time from end of reset to completion of soft-start
is 10.2ms.
Pulling COMP/SD below 0.8V or VCC dropping below
minimum POR initiates another reset.
control feedback loop of the converter.
Pulling COMP/SD to a level below 0.8V disables the
controller. Disabling the ISL6520B causes the oscillator to
stop, the LGATE and UGATE outputs to be held low, and the
softstart circuitry to re-arm. The COMP/SD pin must be
pulled above 0.8V to terminate shutdown. This may be done
through a pullup resistor tied between VCC and COMP/SD.
The recommended range of resistor values to use as the pullup
V COMP/SD
1V/DIV.
V OUT
500mV/DIV.
resistor is between 50k Ω and 100k Ω .
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off.
4
TIME (2ms/DIV.)
FIGURE 1. SOFT START INTERVAL
Current Sinking
The ISL6520B incorporates a MOSFET shoot-through
protection method which allows a converter to sink current
as well as source current. Care should be exercised when
designing a converter with the ISL6520B when it is known
that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating it’s input voltage. This
means that the converter is boosting current into the V CC
FN9083.3
July 23, 2007
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