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参数资料
| 型号： | ISL6522ACB |
| 厂商： | Intersil |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 14-SOIC |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 25°C ~ 70°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
ISL6522A
SS
ISL6522A
BOOT
C BOOT
PHASE
D1
+V IN
Q1
L O
V OUT
? V OSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
V IN
L O
PHASE
C O
V OUT
C SS
GND
+12V
VCC
C VCC
Q2
C O
V E/A
Z FB
-
+
Z IN
ESR
(PARASITIC)
ERROR
REFERENCE
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
AMP
DETAILED COMPENSATION COMPONENTS
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V OUT ) is regulated to the reference voltage level. The error
amplifier (error amp) output (V E/A ) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
C1
C2
R2
Z FB
C3
Z IN
R3
V OUT
modulated (PWM) wave with an amplitude of V IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L O and C O ).
COMP
-
+
FB
R1
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage ? V OSC .
Modulator Break Frequency Equations
ISL6522A
REF
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
3. Place 2 ND Zero at Filter ’s Double Pole
4. Place 1 ST Pole at the ESR Zero
F LC = ---------------------------------------
F ESR = ---------------------------------------------
1
2 π ? L O ? C O
1
2 π ? ( ESR ? C O )
5. Place 2 ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier ’s Open-Loop Gain
F Z1 = ----------------------------------
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
F P2 = ----------------------------------
F Z2 = ------------------------------------------------------
The compensation network consists of the error amplifier
(internal to the ISL6522A) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees . The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1 1
2 π ? R 2 ? C1 C1 ? C2
? C1 + C2 ?
1 1
2 π ? ( R1 + R3 ) ? C3 2 π ? R3 ? C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter ’s Double Pole
(~75% F LC )
8
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F P2 with the capabilities of the error
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
FN9122.2
April 13, 2005
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相关代理商/技术参数 |
参数描述 |
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| ISL6522ACB-T | 功能描述:IC REG CTRLR BST PWM VM 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6522ACR | 功能描述:IC REG CTRLR BST PWM VM 16-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6522ACR-T | 功能描述:IC REG CTRLR BST PWM VM 16-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6522BCB | 功能描述:IC REG CTRLR BST PWM VM 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6522BCB-T | 功能描述:IC REG CTRLR BST PWM VM 14-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
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