参数资料
型号: ISL6522BCB
厂商: Intersil
文件页数: 9/15页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 14-SOIC
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 10.8 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 管件
ISL6522B
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
OSC
DRIVER
V IN
-
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C SS
close to the SS pin because the internal current source is
only 10 μ A. Provide local V CC decoupling between VCC and
GND pins. Locate the capacitor, C BOOT as close as practical
to the BOOT and PHASE pins.
? V OSC
PWM
COMPARATOR
+
Z FB
DRIVER
L O
PHASE
C O
ESR
(PARASITIC)
V OUT
V E/A
-
ISL6522B
BOOT
C BOOT
PHASE
D1
+V IN
Q1
L O
V OUT
+
ERROR
AMP
Z IN
REFERENCE
SS
+12V
Q2
C O
DETAILED COMPENSATION COMPONENTS
C SS
GND
VCC
C VCC
C1
C2
R2
Z FB
C3
Z IN
R3
V OUT
COMP
R1
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
ISL6522B
-
+
REF
FB
F ESR = ---------------------------------------------
F LC = ---------------------------------------
(V OUT ) is regulated to the reference voltage level. The error
amplifier (error amp) output (V E/A ) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V IN at the
PHASE node. The PWM wave is smoothed by the output filter
(L O and C O ).
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage ? V OSC .
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
1 1
2 π ? L O ? C O 2 π ? ( ESR ? C O )
The compensation network consists of the error amplifier
(internal to the ISL6522B) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees . The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F Z1 = ----------------------------------
F P1 = -------------------------------------------------------
2 π ? R2 ? ? ---------------------- ?
F Z2 = ------------------------------------------------------
F P2 = ----------------------------------
1
2 π ? R 2 ? C1
1
2 π ? ( R1 + R3 ) ? C3
1
C1 ? C2
? C1 + C2 ?
1
2 π ? R3 ? C3
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter ’s Double Pole
(~75% F LC )
9
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