参数资料
型号: ISL6522BIRZ-TS2698
厂商: Intersil
文件页数: 12/15页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 16-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 10.8 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 带卷 (TR)
ISL6522B
+12V
D BOOT
+12V
VCC
+
V D
-
+5V OR +12V
VCC
+5V OR LESS
ISL6522B
BOOT
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC - V D
ISL6522B
BOOT
UGATE
PHASE
Q1
NOTE:
V G-S ≈ V CC - 5V
+5V
PVCC OR +12V
PVCC
+5V
OR +12V
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V CC . This option should only be used in
converter systems where the main input voltage is +5V DC or
less. The peak upper gate-to-source voltage is
approximately V CC less the input supply. For +5V main
power and +12V DC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PV CC .
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT V CC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.
12
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