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| 型号： | ISL6522CV-T |
| 厂商： | Intersil |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 14-TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 100% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
ISL6522
switch realizes most of the switching losses when the converter
is sinking current (see the equations below).
Losses while Sourcing Current
+12V
VCC
D BOOT
+ -
V D
+5V OR +12V
P UPPER = Io × r DS ( ON ) × D + --- ? Io × V IN × t SW × F S
2 1
2
P LOWER = Io 2 x r DS(ON) x (1 - D)
Losses while Sinking Current
ISL6522
BOOT
UGATE
PHASE
C BOOT
Q1
NOTE:
V G-S ≈ V CC - V D
P UPPER = Io 2 x r DS(ON) x D
+5V
P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ? Io × V IN × t SW × F S
2 1
2
Where: D is the duty cycle = V OUT / V IN ,
t SW is the switching interval, and
F S is the switching frequency.
-
+
PVCC OR +12V
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL6522 and do not
heat the MOSFETs. However, large gate-charge increases
the switching interval, t SW which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
GND
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 10 shows the upper gate drive supplied by a direct
connection to V CC . This option should only be used in
converter systems where the main input voltage is +5V DC or
less. The peak upper gate-to-source voltage is approximately
V CC less the input supply. For +5V main power and +12V DC
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage rating
exceeds the maximum voltage applied to PV CC .
Standard-gate MOSFETs are normally recommended for
use with the ISL6522. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
+12V
VCC
+5V OR LESS
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V CC . The boot capacitor, C BOOT
develops a floating supply voltage referenced to the PHASE
ISL6522
BOOT
UGATE
PHASE
+5V
OR +12V
PVCC
Q1
NOTE:
V G-S ≈ V CC - 5V
pin. This supply is refreshed each cycle to a voltage of V CC
less the boot diode drop (V D ) when the lower MOSFET, Q2
turns on. A logic-level MOSFET can only be used for Q1 if
-
+
LGATE
PGND
Q2
D2
NOTE:
V G-S ≈ PVCC
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V CC . For Q2, a
logic-level MOSFET can be used if its absolute gate-to-
source voltage rating exceeds the maximum voltage applied
to PVCC.
11
GND
FIGURE 10. UPPER GATE DRIVE - DIRECT V CC DRIVE OPTION
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
FN9030.8
March 10, 2006
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