参数资料
型号: ISL6526EVAL2
厂商: Intersil
文件页数: 3/8页
文件大小: 0K
描述: EVALUATION BOARD QFN ISL6526
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 2.5V
电流 - 输出: 5A
输入电压: 3.3 ~ 5 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6526
AN1021
V OUT at 300kHz
10mV/DIV
V OUT at 600kHz
10mV/DIV
5 μ s/DIV
FIGURE 5. OUTPUT RIPPLE VOLTAGE
Transient Performance
Figures 6 and 7 show the response of the output when
subjected to sourcing and sinking transient loading,
respectively.
V OUT at 300kHz
10mV/DIV
V OUT at 600kHz
10mV/DIV
Load Current
Lossless Output Voltage Droop
Droop is an intentional sag in the output voltage that is
proportional to the output current. Although not necessary
for proper circuit operation, utilizing droop allows the
dynamic regulation to be improved by taking advantage of
static regulation requirements and expanding the available
headroom for transient edge output excursions. In practical
applications that are compared to a non-droop
implementation, the droop implementation requires fewer
output capacitors or better regulation with the same type and
number of output capacitors.
By moving the regulation point ahead of the output inductor
(at the PHASE node), droop becomes equal to the average
voltage drop across the output inductor’s DC resistance as
well as any distributed resistance. The droop circuitry is
simply an RC low pass filter placed across the output
inductor. This filter must have the same time constant that
the output inductor and it’s corresponding DCR have. The
design must be careful to include any parasitic impedances
of the PC board if the DCR of the inductor is very low.
The ISL6526/27 evaluation board does not have any
component footprints that would allow an implementation of
droop. This section is included in this application note as a
guideline in the event that droop is necessary in a design
utilizing the ISL6526 or ISL6527. Figure 8 shows a
schematic of the power stage and Type III compensation
network of an ISL6526/27 regulator with droop. The droop
ISL6526
OR
2A/DIV
ISL6527
VIN
200 μ s/DIV
FIGURE 6. SOURCING TRANSIENT
UGATE
Q U
L OUT
DCR
R parasitic
V OUT
LGATE
Q L
R D
+
C OUT
C D
V OUT at 300kHz
10mV/DIV
FB
R FB
V OUT at 600kHz
10mV/DIV
COMP
R OS
Load Current
2A/DIV
200 μ s/DIV
FIGURE 7. SINKING TRANSIENT
FIGURE 8. DROOP IMPLEMENTATION
circuitry is represented by resistor R D and capacitor C D . The
output of this low pass filter is fed directly into the feedback
compensation network of the regulator. To insure symmetric
output voltage excursions about the nominal voltage in
response to load transients, the output voltage should be
programmed to be above the nominal level by half the
calculated droop.
3
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