参数资料
型号: ISL6527CRZ-T
厂商: Intersil
文件页数: 5/16页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 16-QFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 325kHz
占空比: 100%
电源电压: 2.97 V ~ 3.63 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 带卷 (TR)
ISL6527, ISL6527A
Functional Pin Description
14 LD (SOIC)
TOP VIEW
UGATE
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive
GND 1
LGATE 2
CPVOUT 3
CT1 4
CT2 5
OCSET/SD 6
FB 7
16 LD 5X5 (QFN)
TOP VIEW
14 UGATE
13 BOOT
12 PHASE
11 VCC
10 CPGND
9 REF_IN
8 COMP
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
BOOT
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
LGATE
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
CPVOUT 1
CT1 2
CT2 3
OCSET/SD 4
16
15
14
13
12 PHASE
11 VCC
10 CPGND
9
NC
OCSET/SD
Connect a resistor (R OCSET ) from this pin to the drain of the
upper MOSFET (V IN ). R OCSET , an internal 20μA current
source (I OCSET ), and the upper MOSFET ON-resistance
(r DS(ON) ) set the converter overcurrent (OC) trip point
according to Equation 1:
I PEAK = -------------------------------------------------
5
6
7
8
I OCSET xR OCSET
r DS ( ON )
(EQ. 1)
An overcurrent trip cycles the soft-start function.
VCC
This pin provides the bias supply for the ISL6527, ISL6527A.
Connect a well-decoupled 3.3V supply to this pin.
COMP and FB
COMP and FB are two of the three available external pins of
the error amplifier. The FB pin is the inverting input of the
internal error amplifier and the COMP pin is the error
amplifier output. These pins are used to compensate the
voltage-control feedback loop of the converter.
REF_IN
This pin is the third available external pin of the error
amplifier and represents the non-inverting input to the error
amplifier. Connect the desired reference voltage to this pin.
Voltage applied to this pin must not exceed 1.5V.
GND
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available.
PHASE
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
5
Pulling OCSET/SD to a voltage level below 0.8V disables
the controller. Disabling the ISL6527, ISL6527A causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm.
CT1 and CT2
These pins are the connections for the external charge
pump capacitor. A minimum of a 0.1μF ceramic capacitor is
recommended for proper operation of the IC.
CPVOUT
This pin represents the output of the charge pump. The
voltage at this pin is the bias voltage for the IC. Connect a
decoupling capacitor from this pin to ground. The value of
the decoupling capacitor should be at least 10x the value of
the charge pump capacitor. This pin may be tied to the
bootstrap circuit as the source for creating the BOOT
voltage.
CPGND
This pin represents the signal and power ground for the
charge pump. Tie this pin to the ground island/plane through
the lowest impedance connection available.
FN9056.10
November 18, 2008
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