参数资料
| 型号： | ISL6531CBZ |
| 厂商： | Intersil |
| 文件页数： | 12/17页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER INTEL 24SOIC |
| 标准包装： | 30 |
| 应用： | 控制器，Intel Pentium? III，IV |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 2 |
| 输出电压： | 2.5V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC |
| 包装： | 管件 |
ISL6531
The compensation network consists of the error amplifier
(internal to the ISL6531) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 3 , C 1 , C 2 , and C 3 ) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F LC ).
3. Place second zero at filter’s double pole.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin
V TT Feedback Compensation
To ease design and reduce the number of small-signal
components required, the V TT regulator is internally
compensated. The only stability criteria that needs to be
met relates the minimum value of the inductor to the
equivalent ESR of the output capacitor bank as shown in
the following equation:
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
L OUT ( MIN ) ≥ 20 ? ( 10
– 6
) × ESR OUT × V IN
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
where
L OUT(MIN) = minimum output inductor value at full output
current
F Z1 = ----------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
F Z2 = -------------------------------------------------------
F P2 = ------------------------------------
1
2 π × R 2 × C 2
1
2 π x ( R 1 + R 3 ) x C 3
1
? C 1 x C 2 ?
? C 1 + C 2 ?
1
2 π x R 3 x C 3
ESR OUT = equivalent ESR of the output capacitor bank
V IN = Input voltage of the converter
The design procedure for this output should follow the
following steps:
1. Choose the number and type of output capacitors to meet
the output transient requirements based on the dynamic
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F P2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 9 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain..
loading characteristics of the output.
2. Determine the equivalent ESR of the output capacitor
bank and calculate the minimum output inductor value.
3. Verify that the chosen inductor meets this minimum value
criteria at full output load. It is recommended that the
chosen inductor be no more than 30% saturated at full
output load.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
? V IN ?
100
80
F Z1
F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
20 log ? ---------------- ?
? V OSC ?
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
60
capacitors and careful layout.
40
20
COMPENSATION
GAIN
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
20 log ? -------- ?
0
-20
-40
R2
? R1 ?
MODULATOR
GAIN
F LC
F ESR
LOOP GAIN
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
-60
10
100
1K
10K
100K
1M
10M
High frequency decoupling capacitors should be placed as
FREQUENCY (Hz)
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
12
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
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